Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 255

Powerquicc family

Table of Contents

The page size is determined by a combination of two fields: the page-size (PS) field in the level-one

descriptor and the small-page-size (SPS) field in the level-two descriptor.

fields select the page size.

Level 1 [PS]

Programming Model

All MMU programming model registers are supervisor-level SPRs that are accessed by using mtspr and

mfspr. Attempting to access these SPRs in user mode causes a program exception. The tlbie and tlbia

instructions can be used to invalidate TLBs. MMU registers should be accessed when both MSR[IR] = 0

and MSR[DR] = 0. No similar restriction exists for tlbie and tlbia.

lists the MPC885-specific MMU registers and indicates the sections that describe them. These

SPRs should be accessed when both instruction and data address translation is disabled.

IMMU control register

DMMU control register

IMMU effective number register

DMMU effective number register

IMMU tablewalk control register

DMMU tablewalk control register

IMMU real (physical) page number port

DMMU real (physical) page number register

Freescale Semiconductor

Table 8-5. Page Size Selection

Level 2 [SPS]

Table 8-6. MPC885-Specific MMU SPRs

Control Registers

TLB Source Registers

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Memory Management Unit

shows how the two