Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 18

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Number
15.3.6 Memory Bank Protection Status ................................................................................ 15-8
15.3.7 UPM-Specific Registers ............................................................................................ 15-8
15.3.8 GPCM-Specific Registers.......................................................................................... 15-8
15.4 Register Descriptions ..................................................................................................... 15-8
15.4.1 Base Registers (BRx)................................................................................................. 15-8
15.4.2 Option Registers (ORx) ........................................................................................... 15-11
15.4.3 Memory Status Register (MSTAT) .......................................................................... 15-13
15.4.4 Machine A Mode Register/Machine B Mode Registers (MxMR) .......................... 15-14
15.4.5 Memory Command Register (MCR) ....................................................................... 15-15
15.4.6 Memory Data Register (MDR) ................................................................................ 15-17
15.4.7 Memory Address Register (MAR) .......................................................................... 15-17
15.4.8 Memory Periodic Timer Prescaler Register (MPTPR) ............................................ 15-18
15.5 General-Purpose Chip-Select Machine (GPCM)......................................................... 15-18
15.5.1 Timing Configuration .............................................................................................. 15-19
15.5.1.1 Chip-Select Assertion Timing ............................................................................. 15-20
15.5.1.2 Chip-Select and Write Enable Deassertion Timing ............................................. 15-21
15.5.1.3 Relaxed Timing.................................................................................................... 15-23
15.5.1.4 Output Enable (OE) Timing ................................................................................ 15-26
15.5.1.5 Programmable Wait State Configuration ............................................................. 15-26
15.5.1.6 Extended Hold Time on Read Accesses .............................................................. 15-26
15.5.2 Boot Chip-Select Operation..................................................................................... 15-29
15.5.3 External Asynchronous Master Support .................................................................. 15-30
15.5.4 Special Case: Bursting with External Transfer Acknowledge:................................ 15-31
15.6 User-Programmable Machines (UPMs)....................................................................... 15-32
15.6.1 Requests ................................................................................................................... 15-33
15.6.1.1 Internal/External Memory Access Requests........................................................ 15-33
15.6.1.2 UPM Periodic Timer Requests ............................................................................ 15-34
15.6.1.3 Software Requests—MCR run Command........................................................... 15-34
15.6.1.4 Exception Requests.............................................................................................. 15-34
15.6.2 Programming the UPM............................................................................................ 15-34
15.6.3 Control Signal Generation Timing........................................................................... 15-35
15.6.4 The RAM Array....................................................................................................... 15-37
15.6.4.1 RAM Words......................................................................................................... 15-38
15.6.4.2 Chip-Select Signals (CSTx)................................................................................. 15-41
15.6.4.3 Byte-Select Signals (BSTx)................................................................................. 15-42
15.6.4.4 General-Purpose Signals (GxTx, G0x)................................................................ 15-43
15.6.4.5 Loop Control (LOOP).......................................................................................... 15-45
15.6.4.6 Exception Pattern Entry (EXEN)......................................................................... 15-46
15.6.4.7 Address Multiplexing (AMX) ............................................................................. 15-46
15.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3) ........................ 15-51
15.6.4.9 Disable Timer Mechanism (TODT)..................................................................... 15-52
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Contents
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor