Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 216

Instruction and Data Caches
considered to have memory-coherency-not-required attributes. Therefore, software must maintain
instruction cache coherency. The MPC885 supports a fast instruction cache invalidate capability as
described in Section 7.3.1.2.5, "Instruction Cache Invalidate All Command."
The instruction cache also implements a lock bit for each cache block that allows instructions to be loaded
into the instruction cache and locked, providing fast and deterministic execution time for critical code
segments. The MPC885 supports commands for locking and unlocking individual cache blocks and for
unlocking all the cache blocks at once.
7.2 Data Cache Organization
The MPC885 data cache is organized as 256 sets of two blocks as shown in Figure 7-2. Each block consists
of four words, two state bits, a lock bit, and an address tag.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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