Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 405

Address type signals reflect the current status of the master originating the access, not necessarily the status
in which the original access to this location has occurred. An example of this situation is when a modified
data cache block is copied back after the privilege level of the processor has been changed since the last
access to the same cache block. A functional usage of the address type signal RSV is for the reservation
protocol described in Section 13.4.9, "Memory Reservation." Table 13-5
encoded by the STS, TS, AT[0:3], PTR, and RSV.
Core/ User/
STS TS CPM Supervisor
(AT0) (AT1)
1 x x
0 x x
x 0 0
1 AT1
Freescale Semiconductor
Table 13-5. Address Types Definition
Reservation/
Instruction/
Program Trace
Data (AT2)
(AT3)
x x
x x
0 0
1
1 0
1
AT2 AT3
MPC885 PowerQUICC Family Reference Manual, Rev. 2
provides the space definition
Program
Reservation
Trace
(RSV)
(PTR)
x 1 1
x x x
0 0 1
1 1 1
0 1 0
1 1 1
0 0 1
1 1 1
0 1 0
1 1 1
1 1
External Bus Interface
Address Space
Definitions
No transfer or not the first
transaction of a transfer
Start of a transaction
Core-initiated, normal
instruction, program trace,
supervisor mode
Core-initiated, normal
instruction, supervisor
mode
Core-initiated, reservation
data, supervisor mode
Core-initiated, normal data,
supervisor mode
Core-initiated, normal
instruction, program trace,
user mode
Core-initiated, normal
instruction, user mode
Core-initiated, reservation
data, user mode
Core-initiated, normal data,
user mode
DMA-initiated, normal,
AT[1:3] user-programmable
(see IDMA and DMA
function code registers)
13-31