Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 352

External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Name
Reset
PE19 Hi-Z
L1TXDB
MII2-TXEN
RMII2-TXEN
PE18 Hi-Z
L1TSYNCA
SMTXD1
MII2-TXD3
PE17 Hi-Z
TIN3
CLK5
BRGO3
SMSYN1
MII2-TXD2
PE16 Hi-Z
L1RCLKB
CLK6
TXD3
MII2-TXCLK
RMII2-REFCLK
PE15 Hi-Z
TGATE1
MII2-TXD1
RMII2-TXD1
PE14 Hi-Z
RXD3
MII2-TXD0
RMII2-TXD0
TCK Hi-Z
DSCK
TMS Pulled up
TDI Pulled up
DSDI
TDO Low
DSDO
TRST Pulled up
MII1_CRS Hi-Z
MII_MDIO Hi-Z
MII1_TXEN Low
12-22
Number Type
T6 Bidirectional
(optional:
open-drain)
R1 Bidirectional
(optional:
open-drain)
W8 Bidirectional
(optional:
open-drain)
T7 Bidirectional
(optional:
open-drain)
W6 Bidirectional General-Purpose I/O Port E Bit 15
V7 Bidirectional General-Purpose I/O Port E Bit 14
U17 Input
V18 Input
T16 Input
T17 Output
3
W18 Input
T11 Input
P19 Bidirectional MII_MDIO—Media-independent interface management data
T5 Output
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
General-Purpose I/O Port E Bit 19
L1TXDB—Transmit data output for the serial interface TDMb.
MII2-TXEN—Media-independent interface 2, transmit enable
RMII2-TXEN—Reduced media-independent interface 2, transmit
enable
General-Purpose I/O Port E Bit 18
L1TSYNCA—Transmit sync input for serial interface TDMa
SMTXD1—SMC1 transmit data output
MII2-TXD3—Media-independent interface 2, transmit data 3
General-Purpose I/O Port E Bit 17
TIN3—Timer 3 external clock input
CLK5—One of eight clock inputs that can be used to clock SCCs
and SMCs
BRGO3—Output clock of BRG3
SMSYN1—SMC1 external sync input
MII2-TXD2—Media-independent interface 2, transmit data 2
General-Purpose I/O Port E Bit 16
L1RCLKB—Receive clock for the serial interface TDMb
CLK6—One of eight clock inputs that can be used to clock SCCs
and SMCs
TXD3—Transmit data output for SCC3
MII2-TXCLK—Media-independent interface 1, transmit clock
RMII2-REFCLK—Reduced media-independent interface 1,
reference clock
TGATE1—Timer 1/timer 2 gate signal
MII2-TXD1—Media-independent interface 2, transmit data 1
RMII2-TXD1—Reduced media-independent interface 2, transmit
data 1
RXD3—Receive data input for SCC3
MII2-TXD0—Media-independent interface 2, transmit data 0
RMII2-TXD0—Reduced media-independent interface 2, transmit
data 0
Provides clock to scan chain logic or for the development port
logic
Controls the scan chain test mode operations
Input serial data for either the scan chain logic or the development
port and determines the operating mode of the development port
at reset
Output serial data for either the scan chain logic or for the
development port
Test reset for the JTAG scan chain logic
MII1_CRS —Media-independent interface 1, carrier receive
sense
MII1_TXEN—Media-independent interface 1, transmit enable
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