Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 728

SCC Asynchronous HDLC Mode and IrDA
25.9 Configuring GSMR and DSR for Asynchronous HDLC
General SCC parameters can be configured as described in
Controllers," except for the following changes to the general SCC mode register and the data
synchronization register.
25.9.1 General SCC Mode Register (GSMR)
Table 25-2 shows asynchronous HDLC-specific information for the GSMR.
Table 25-2. Asynchronous HDLC-Specific GSMR Field Descriptions
Name
IRP Infrared Rx polarity (GSMR_H[13]). Determines the polarity of the received signal when SCC2 uses IrDA
encoding/decoding—for SCC2 only. See
0 Active high polarity. An active high pulse is decoded as 0.
1 Active low polarity. An active low pulse is decoded as 0.
RFW Rx FIFO width (GSMR_H[26])
0 Do not use.
1 Low-latency operation—for character-oriented protocols like UART, BISYNC, and asynchronous HDLC.
The Rx FIFO is 8 bits wide and the Rx FIFO is one-fourth its normal size (4 bytes). This allows each
character to be written to the buffer without waiting for 32 bits to be received.
SIR Serial infrared encoding—for SCC2 only (GSMR_L[0]). Setting SIR activates the serial infrared
coder/encoder. See
TDCR/ Tx/Rx divide clock rate (GSMR_L[14–15/16–17]). For asynchronous HDLC mode, 8×, 16×, or 32× must be
RDCR chosen. Set TDCR = RDCR in most applications.
00 Do not use.
01 8× clock mode (do not use for IrLAP).
10 16× clock mode.
11 32× clock mode (do not use for IrLAP).
25.9.2 Data Synchronization Register (DSR)
The data synchronization register (DSR) is reserved in asynchronous HDLC mode. It should be left in its
reset state of 0x7E7E.
25.10 Programming the Asynchronous HDLC Controller
Asynchronous HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0110. The
asynchronous HDLC controller uses the same buffer and BD data structure as other modes and supports
multibuffer operation. Receive errors are reported through the RxBD; transmit errors are reported through
the TxBD. Status line information (CD and CTS) is reported through the port C pins; a maskable interrupt
is generated when the status of either line changes.
25.11 Asynchronous HDLC Commands
The transmit and receive commands are issued to the CP command register (CPCR).
25-6
Description
Section 25.18, "IrDA Encoder/Decoder (SCC2 Only)."
Section 25.18, "IrDA Encoder/Decoder (SCC2 Only)."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Chapter 21, "Serial Communications
Freescale Semiconductor