Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 890

2
I C Controller
bit masks the corresponding interrupt. Unmasked I2CER bits must be cleared before the CPM clears
internal interrupt requests.
0
Field
Reset
R/W
Addr
This registers are affected by HRESET and SRESET.
Bits Name
0–2 — Reserved and should be cleared.
3 TXE Tx error. Set when an error occurs during transmission.
4 — Reserved and should be cleared.
5 BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer has been sent.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed.
2
32.4.5 I C Command Register (I2COM)
2
The I C command register, shown in
slave mode.
0
Field STR
Reset
R/W
Addr
This register is affected by HRESET and SRESET.
Bits Name
0 STR Start transmit. In master mode, setting STR causes the I
2
I C Tx buffers if they are ready. In slave mode, setting STR when the I
to load the Tx data register from the current Tx buffer (if ready) and start sending when it receives
an address byte that matches the slave address with R/W = 1. STR is always read as a 0.
32-8
Figure 32-9 shows both registers.
2 3
— TXE
0x870(I2CER)/0x874 (I2CMR)
2
Figure 32-9. I C Event/Mask Registers (I2CER/I2CMR)
Table 32-4. I2CER/I2CMR Field Descriptions
Figure 32-10, is used to start I
1
2
Figure 32-10. I C Command Register (I2COM)
Table 32-5. I2COM Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
4 5
— BSY
0000_0000
R/W
Table 32-4 describes the I2CER/I2CMR fields.
Description
2
C transfers and to select master or
—
0000_0000
R/W
0x86C
Table 32-5 describes I2COM fields.
Description
2
C controller to start sending data from the
6 7
TXB RXB
6 7
M/S
2
C controller is idle causes it
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