Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 169

Table 4-10. MPC885-Specific Debug-Level SPRs (continued)
SPR Number
Decimal SPR[5–9] SPR[0–4]
149 00100
150 00100
151 00100
152 00100
153 00100
154 00100
155 00100
156 00100
157 00100
158 00100
159 00100
630 10011
4.1.3.1 Accessing SPRs
All SPRs are accessed using the mtspr and mfspr instructions, regardless of whether they are within the
processor core. To access registers outside of the core, an internal bus tenure occurs using the address lines,
as described in Table 4-11.
Table 4-11. Addresses of SPRs Located Outside of the Core
Address errors in this tenure cause a software emulation exception.
Freescale Semiconductor
Name
10101 DER
10110 COUNTA
10111 COUNTB
11000 CMPE
11001 CMPF
11010 CMPG
11011 CMPH
11100 LCTRL1
11101 LCTRL2
11110 ICTRL
11111 BAR
10110 DPDR
Address Lines
0:17 18:22
0...0 SPR[0–4]
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Serialize Access
Fetch sync on write
Fetch sync on write
Fetch sync on write
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Write: Fetch sync
Read: Sync relative to load/store operations
Fetch sync on write
Write: Fetch sync
Read: Sync relative to load/store operations. See
Section 4.1.2.1, "DAR, DSISR, and BAR Operation."
Read and Write
23:27 28:31
SPR[5–9] 0000
MPC8xx Core Register Set
4-11