Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 264

Memory Management Unit
Bits Name
30 CI Cache-inhibit attribute for the entry
0 Caching is allowed.
1 Caching is inhibited.
31 V Entry valid indication
1
For pages larger than 4 Kbytes in mode 2, PP in bits [22–23,24–25,26–27] must equal the PP in bits [20–21].
8.8.8 MMU Tablewalk Base Register (M_TWB)
The MMU tablewalk base register (M_TWB), shown in
table to be used in hardware-assisted tablewalk mode.
0
Field
Reset
R/W
SPR
Table 8-14 describes M_TWB fields.
Bits Name
0–19 L1TB Tablewalk level-one base value
20–29 L1INDX Level-one table index. Ignored on write, returns MD_EPN[0–9] on read when MD_CTR[TWAM] =
1. Returns MD_EPN[2–11] on read when MD_CTR[TWAM] = 0
30–31 — Reserved. Ignored on write, returns 0 on read.
8.8.9 MMU Current Address Space ID Register (M_CASID)
The MMU current address space ID register (M_CASID), shown in
current EA with the ASID field in the TLB entry when searching for a match.
0
Field
Reset
R/W
SPR
Figure 8-14. MMU Current Address Space ID Register (M_CASID)
8-22
Table 8-13. MD_RPN Field Descriptions (continued)
Mode 2
L1TB
Figure 8-13. MMU Tablewalk Base Register (M_TWB)
Table 8-14. M_TWB Field Descriptions
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Mode 1 or Mode 3
Figure 8-13, contains a pointer to the level-one
19 20
—
R/W
796
Description
Figure 8-14, is used to compare the
—
R/W
793
29 30 31
L1INDX —
00
27 28 31
CASID
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