Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 22

Paragraph
Number
19.3.4.2 Auto-Buffering and Buffer-Chaining .................................................................. 19-12
19.3.5 IDMA CP Commands.............................................................................................. 19-13
19.3.6 IDMA Channel Operation ....................................................................................... 19-13
19.3.6.1 Activating an IDMA Channel.............................................................................. 19-13
19.3.6.2 Suspending an IDMA Channel............................................................................ 19-13
19.3.7 IDMA Interface Signals—DREQ and SDACK....................................................... 19-14
19.3.7.1 IDMA Requests for Memory/Memory Transfers ................................................ 19-14
19.3.7.2 IDMA Requests for Peripheral/Memory Transfers ............................................. 19-14
19.3.7.2.1 Level-Sensitive Requests................................................................................. 19-15
19.3.7.2.2 Edge-Sensitive Requests.................................................................................. 19-15
19.3.8 IDMA Transfers—Dual-Address and Single-Address ............................................ 19-15
19.3.8.1 Dual-Address (Dual-Cycle) Transfer................................................................... 19-15
19.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By)............................................... 19-16
19.3.9 External Recognition of an IDMA Transfer ............................................................ 19-18
19.3.10 Interrupts During an IDMA Bus Transfer ............................................................... 19-18
20.1 SI Features ..................................................................................................................... 20-2
20.2 TSA Implementation...................................................................................................... 20-4
20.2.1 TSA Signals ............................................................................................................... 20-7
20.2.2 Enabling Connections to the TSA ............................................................................. 20-8
20.2.3 SI RAM...................................................................................................................... 20-8
20.2.3.1 Disabling and Reenabling the TSA ....................................................................... 20-9
20.2.3.2 One TDM Channel with Static Frames.................................................................. 20-9
20.2.3.3 Two TDM Channels with Static Frames................................................................ 20-9
20.2.3.4 SI RAM Dynamic Changes ................................................................................. 20-10
20.2.3.5 One TDM Channel with Dynamic Frames.......................................................... 20-12
20.2.3.6 Two TDM Channels with Dynamic Frames ........................................................ 20-12
20.2.3.7 Programming the SI RAM................................................................................... 20-13
20.2.3.8 SI RAM Programming Example ......................................................................... 20-15
20.2.4 The SI Registers....................................................................................................... 20-15
20.2.4.1 SI Global Mode Register (SIGMR) ..................................................................... 20-15
20.2.4.2 SI Mode Register (SIMODE) .............................................................................. 20-17
20.2.4.3 SI Clock Route Register (SICR).......................................................................... 20-22
20.2.4.4 SI Command Register (SICMR).......................................................................... 20-24
20.2.4.5 SI Status Register (SISTR) .................................................................................. 20-24
20.2.4.6 SI RAM Pointer Register (SIRP)......................................................................... 20-25
20.2.5 IDL Bus Implementation ......................................................................................... 20-27
20.2.5.1 ISDN Terminal Adaptor Application................................................................... 20-27
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Contents
Title
Chapter 20
Serial Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor