Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 399

Powerquicc family

Table of Contents

lists the bytes required on the data bus for read cycles.

Denotes a byte not required during that read cycle.

lists data transfer patterns for write cycles when the MPC885 initiates accesses.

Denotes a byte not required during that read cycle.

Arbitration Phase

The external bus design provides for a single bus master at any one time, either the MPC885 or an external

device. The arbitration of external bus devices contending for bus mastership may be handled either by an

external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for

one external bus master besides the MPC885. The arbitration configuration (external or internal) is set at

system reset. See

Section 15.8, "External Master Support."

Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. A device needing

the bus asserts BR and waits for the arbiter to assert BG. The new master must look at BB to ensure that

no other master is driving the bus before it can assert BB to assume bus mastership. (Note that the internal

Freescale Semiconductor

Table 13-2. Data Bus Requirements for Read Cycles

Table 13-3. Data Bus Contents for Write Cycles

MPC885 PowerQUICC Family Reference Manual, Rev. 2

External Data Bus Pattern

External Bus Interface