Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 21

Paragraph
Number
18.6.2 RISC Microcode Development Support Control Register (RMDS) ......................... 18-6
18.6.3 CP Command Register (CPCR)................................................................................. 18-7
18.6.4 CP Commands ........................................................................................................... 18-8
18.6.4.1 CP Command Examples ...................................................................................... 18-10
18.6.4.2 CP Command Execution Latency........................................................................ 18-10
18.7 Dual-Port RAM............................................................................................................ 18-10
18.7.1 System RAM and Microcode Packages................................................................... 18-12
18.7.2 The Buffer Descriptor (BD)..................................................................................... 18-13
18.7.3 Parameter RAM ....................................................................................................... 18-13
18.8 The RISC Timer Table................................................................................................. 18-14
18.8.1 RISC Timer Table Scan Algorithm.......................................................................... 18-15
18.8.2 The set timer Command........................................................................................... 18-15
18.8.3 RISC Timer Table Parameter RAM and Timer Table Entries ................................. 18-15
18.8.3.1 RISC Timer Command Register (TM_CMD) ..................................................... 18-16
18.8.3.2 RISC Timer Table Entries.................................................................................... 18-17
18.8.4 RISC Timer Event Register (RTER)/Mask Register (RTMR) ................................ 18-17
18.8.5 PWM Mode.............................................................................................................. 18-18
18.8.6 RISC Timer Initialization ........................................................................................ 18-18
18.8.7 RISC Timer Interrupt Handling ............................................................................... 18-19
18.8.8 Using the RISC Timers to Track CP Loading ......................................................... 18-19
19.1 SDMA Channels ............................................................................................................ 19-1
19.1.1 SDMA Transfers........................................................................................................ 19-2
19.1.2 U-Bus Arbitration and the SDMA Channels ............................................................. 19-3
19.2 SDMA Registers ............................................................................................................ 19-4
19.2.1 SDMA Configuration Register (SDCR) .................................................................... 19-4
19.2.2 SDMA Status Register (SDSR) ................................................................................. 19-5
19.2.3 SDMA Mask Register (SDMR)................................................................................. 19-5
19.2.4 SDMA Address Register (SDAR) ............................................................................. 19-6
19.3 IDMA Emulation ........................................................................................................... 19-6
19.3.1 IDMA Features .......................................................................................................... 19-6
19.3.2 IDMA Parameter RAM ............................................................................................. 19-7
19.3.3 IDMA Registers......................................................................................................... 19-7
19.3.3.1 DMA Channel Mode Registers (DCMR) .............................................................. 19-8
19.3.3.2 IDMA Status Registers (IDSR1 and IDSR2) ........................................................ 19-9
19.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2)....................................................... 19-9
19.3.4 IDMA Buffer Descriptors (BD)................................................................................. 19-9
19.3.4.1 Function Code Registers—SFCR and DFCR...................................................... 19-12
Freescale Semiconductor
Contents
Title
Chapter 19
SDMA Channels and IDMA Emulation
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
xxi