Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 785

28.3.1.4 End of Frame Detection
An end of frame cannot be detected in the transparent data stream since there is no defined closing flag in
transparent mode. Therefore, if framing is needed, the user must use the CD line to alert the transparent
controller of an end of frame.
28.3.2 Synchronization and the TSA
A transparent-mode SCC using the time-slot assigner can synchronize either on a user-defined in-line
pattern or by inherent synchronization.
Note that when using the TSA, a newly-enabled transmitter sends from 10 to 15 frames of idles before
sending the actual transparent data due to start-up requirements of the TDM. Therefore, when loop-back
testing through the TDM, expect to receive several bytes of 0xFF before the actual data.
28.3.2.1 In-line Synchronization Pattern
The receiver can be programmed to begin receiving data into the receive buffers only after a specified data
pattern arrives. To synchronize on an in-line pattern:
• Set GSMR_H[SYNL].
• Program the DSR with the desired pattern.
• Clear GSMR_H[CDP].
• Set GSMR_H[CTSP, CTSS, CDS].
If GSMR_H[TXSY] is also used, the transmitter begins transmission eight clocks after the receiver
achieves synchronization.
28.3.2.2 Inherent Synchronization
Inherent synchronization assumes synchronization by default when the channel is enabled; all data sent
from the TDM to the SCC is received. To implement inherent synchronization:
• Set GSMR_H[CDP, CDS, CTSP, CTSS].
If these bits are not set, the received bit stream will be bit-shifted. The SCC loses the first received bit
because CD and CTS are treated as asynchronous signals.
28.4 CRC Calculation in Transparent Mode
The CRC calculations follow the ITU/IEEE standard. The CRC is calculated on the transmitted data
stream; that is, from lsb to msb for non-bit-reversed (GSMR_H[REVD] = 0) and from msb to lsb for
bit-reversed (GSMR_H[REVD] = 1) transmission. The appended CRC is sent msb to lsb.When receiving,
the CRC is calculated as the incoming bits arrive. The optional reversal of data (GSMR_H[REVD] = 1) is
done just before data is stored in memory (after the CRC calculation).
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SCC Transparent Mode
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