Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 483

The uppermost byte select (BS0) indicates that D[0:7] contains valid data during a cycle. Likewise, BS1
indicates that D[8:15] contains valid data, BS2 indicates that D[16:23] contains valid data, and BS3
indicates that D[24:31] contains valid data during a cycle.
16-, and 8-bit accesses. Note that for a periodic timer request and a memory command request, the BS
signals are determined only by the port size of the bank.
Transfer
TSIZ
Size
Byte 0 1
0 1
0 1
0 1
Half-Word 1 0
1 0
Word 0 0
15.6.4.4 General-Purpose Signals (G x T x , G0 x )
The general-purpose signals (GPL[1:5]) have two bits in the RAM word that define the logical value of
the signal to be changed at the falling edge of GCLK1_50 or GCLK2_50. GPL0 has two 2-bit fields that
perform this function plus an additional function explained below. GPL5 and GPL0 offer the following
enhancements beyond the other GPLx signals:
• GPL5 can be controlled during phase 4 of the first clock cycle according to the value of G5LS, as
shown in Figure
master), which can speed up the memory interface, particularly when GPL5 is used as a control
signal for external address multiplexers.
Freescale Semiconductor
Table 15-15. Enabling Byte-Selects
Address 32-Bit Port Size
A30 A31 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3
0 0 X
0 1 X
1 0 X
1 1
0 0 X X
1 0 X
0 0 X X X
15-42. This allows it to assert earlier (simultaneous with TS, for an internal
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 15-15 shows how BS signals affect 32-,
16-Bit Port Size
X
X
X
X X
X X
X X X
X X X
Memory Controller
8-Bit Port Size
X
X
X
X
X
X
X
15-43