Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 250

Memory Management Unit
— To define four different 1-Kbyte pages, create four level-two descriptors, but set the subpage
validity flags such that: entry one = 0b1000, entry two = 0b0100, entry three = 0b0010, entry
four = 0b0001. All other fields of the level-two descriptor can be set differently for each of
these entries.
— To define two different 2-Kbyte pages, create four level-two descriptors, but set the subpage
validity flags in pairs such that: entry one = 0b1100, entry two = 0b1100, entry three = 0b0011,
entry four = 0b0011. The other fields of the 'paired' level-two descriptors must be the same for
each of the pairs.
Other combinations are also possible.
This mode is the most complex and the most inefficient in memory size (that is, MMU tables are
approximately four times larger). However, it allows the most detailed resolution of protection with
full functionality.
IMMUs and DMMUs can use different modes; the IMMU could use mode 1 and the DMMU could use
mode 2, or vice versa. However, if mode 3 is desired, both MMUs must be in mode 3.
8.6 Memory Attributes
Memory attributes defined by the PowerPC architecture are implemented as follows:
• Reference and change bit updates—The MPC885 does not generate an exception for an R
(reference) bit update. In fact, there is no entry for an R bit in the TLB.
The change bit (C) is bit 23 in the level-two descriptor, described in
(changed) bits, but hardware treats the C bit (negated) as a write-protect attribute. Therefore,
attempting to write to a page marked unmodified invalidates that entry and causes an
implementation-specific DTLB error exception. If change bits are not needed, set the C bit to one
by default in the PTEs.
• Memory control attributes—The MPC885 supports cache inhibit (CI), writethrough (WT), and
guarded (G) attributes, defined in the PowerPC Virtual Environment Architecture (VEA). The
memory coherence (M) attribute is not supported; to ensure memory coherency, configure the page
as cache-inhibited.
attributes in the MPC885.
The G attribute is used to map I/O devices that are sensitive to speculative (out-of-order) accesses.
An attempted speculative access to a page marked guarded (G = 1) stalls until either the access is
nonspeculative or is canceled by the core. Attempting to fetch from guarded memory causes an
implementation-specific instruction TLB error interrupt.
8.7 Translation Table Structure
The MMU hardware supports a two-level software tablewalk. Other table structures are not precluded.
Figure 8-4 shows the two-level translation table when MD_CTR[TWAM] = 1 (4-Kbyte resolution of
protection).
8-8
Chapter 7, "Instruction and Data Caches,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 8-4. Software updates C
describes the effects of CI and WT
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