Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 340

External Signals
Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Name
Reset
IP_A2 Hi-Z
IOIS16_A
UTPB_Split[2]
IP_A(3) Hi-Z
UTPB_Split[3]
IP_A(4) Hi-Z
UTPB_Split[4]
IP_A(5) Hi-Z
UTPB_Split[5]
IP_A(6) Hi-Z
UTPB_Split[6]
IP_A(7) Hi-Z
UTPB_Split[7]
ALE_B See
DSCK Table 12-3
AT1
12-10
Number Type
F4 Input Input Port A 2—This input signal is monitored by the MPC885 and
its value and changes are reported in the PIPR and PSCR of the
PCMCIA interface.
I/O Device A is 16 Bits Ports Size—This input signal is monitored
by the MPC885 when a transaction under the control of the
PCMCIA interface is initiated to an I/O region in socket A of the
PCMCIA space.
UTPB_Split[2]—This input signal is used as Rx data in split bus
mode only.
E3 Input Input Port A 3—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[3]—This input signal is used as Rx data in split bus
mode only.
D2 Input Input Port A 4—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[4]—This input signal is used as Rx data in split bus
mode only.
D1 Input Input Port A 5—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface
UTPB_Split[5]—This input signal is used as Rx data in split bus
mode only.
E2 Bidirectional Input Port A 6—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[6]—This input signal is used as Rx data in split bus
mode only.
D3 Input Input Port A 7—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[7]—This input signal is used as Rx data in split bus
mode only. This is the most-significant bit of the UTPB_Aux bus.
D8 Bidirectional Address Latch Enable B—This output is asserted when the
three-state MPC885 initiates an access to a region under the control of the
PCMCIA socket B interface.
Development Serial Clock—This input is the clock for the debug
port interface.
Address Type 1—The MPC885 drives this bidirectional
three-state line when it initiates a transaction on the external bus.
When the transaction is initiated by the core, it indicates if the
transfer is for user or supervisor state. This signal is not used for
transactions initiated by external masters.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor