Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 504

Memory Controller
3. Translate the timing diagrams into RAM words for each type of memory access. The bottom half
of the figures represent the RAM array contents that handle each of the possible cycles and each
column represents a different word in the RAM array. A blank cell in the figures indicates a don't
care bit, which is typically programmed to logic 1 to conserve power.
4. Define the UPM parameters that control the memory system in the following sequence. For
additional details, see
— Program the RAM array using MCR and MDR. The RAM word must be written into the MDR
before a
WRITE
— Initialize the option and base registers of the specific bank according to the address mapping
of the DRAM device chosen.
— Use ORx[MS] to select the machine to control the cycles. Notice that ORx[SAM] determines
address multiplexing for the first clock cycle and subsequent cycles are controlled by the UPM
RAM words. Also notice that the AMX field in the UPM RAM word controls address
multiplexing for the next clock cycle rather than the current one.
— Program MAMR to select the number of columns and refresh timer parameters.
Register
BR1 MS
PS
WP
MPTPR PTP
MAMR PTA
PTAE
AMA
DSA
GPLA4DIS
RLFA
WLFA
OR1 SAM
BIH
15-64
Table 15-20.
command is issued to the MCR. Repeat this step for all RAM word entries.
Table 15-20. UPMA Register Settings
Field Value
10
00
0
0010_0000
0000_1100
1
001
01
0
0011
0011
1
0
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Comments
Selects UPMA
Selects 32-bit bus width
Allows read and write accesses
Prescaler divided by two
15.6 µs at a 25-MHz clock
Enables periodic timer A
Selects nine column address pins
Selects two disable timer clock cycles
Disables the UPWAITA signal
Selects three loop iterations for read
Selects three loop iterations for write
Selects column address on first cycle
Supports burst accesses
Freescale Semiconductor