Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 12

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Number
7.6.1 Data Cache Load Hit.................................................................................................. 7-23
7.6.2 Data Cache Read Miss............................................................................................... 7-23
7.6.3 Write-Through Mode ................................................................................................. 7-24
7.6.3.1 Data Cache Store Hit in Write-Through Mode...................................................... 7-24
7.6.3.2 Data Cache Store Miss in Write-Through Mode ................................................... 7-24
7.6.4 Write-Back Mode....................................................................................................... 7-25
7.6.4.1 Data Cache Store Hit in Write-Back Mode ........................................................... 7-25
7.6.4.2 Data Cache Store Miss in Write-Back Mode......................................................... 7-25
7.6.5 Data Accesses to Caching-Inhibited Memory Regions ............................................. 7-26
7.6.6 Atomic Memory References...................................................................................... 7-26
7.7 Cache Initialization after Reset...................................................................................... 7-27
7.8 Debug Support ............................................................................................................... 7-27
7.8.1 Instruction and Data Cache Operation in Debug Mode............................................. 7-27
7.8.2 Instruction and Data Cache Operation with a Software Monitor Debugger.............. 7-28
8.1 Features ............................................................................................................................ 8-1
8.2 PowerPC Architecture Compliance ................................................................................. 8-2
8.3 Address Translation ......................................................................................................... 8-2
8.3.1 Translation Disabled .................................................................................................... 8-2
8.3.2 Translation Enabled ..................................................................................................... 8-3
8.3.3 TLB Operation............................................................................................................. 8-5
8.4 Using Access Protection Groups ..................................................................................... 8-6
8.5 Protection Resolution Modes........................................................................................... 8-7
8.6 Memory Attributes........................................................................................................... 8-8
8.7 Translation Table Structure .............................................................................................. 8-8
8.7.1 Level-One Descriptor ................................................................................................ 8-11
8.7.2 Level-Two Descriptor ................................................................................................ 8-12
8.7.3 Page Size.................................................................................................................... 8-13
8.8 Programming Model ...................................................................................................... 8-13
8.8.1 IMMU Control Register (MI_CTR) .......................................................................... 8-14
8.8.2 DMMU Control Register (MD_CTR) ....................................................................... 8-15
8.8.3 IMMU/DMMU Effective Page Number Register (Mx_EPN) .................................. 8-16
8.8.4 IMMU Tablewalk Control Register (MI_TWC) ....................................................... 8-17
8.8.5 DMMU Tablewalk Control Register (MD_TWC) .................................................... 8-18
8.8.6 IMMU Real Page Number Register (MI_RPN) ........................................................ 8-19
8.8.7 DMMU Real Page Number Register (MD_RPN) ..................................................... 8-20
8.8.8 MMU Tablewalk Base Register (M_TWB)............................................................... 8-22
8.8.9 MMU Current Address Space ID Register (M_CASID)........................................... 8-22
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Contents
Title
Chapter 8
Memory Management Unit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor