Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 749

Bits Name
9 DRT Disable receiver while sending. DRT should not be set for typical BISYNC operation.
0 Normal operation
1 As the SCC sends data, the receiver is disabled and gated by the internal RTS signal. This helps
if the BISYNC channel is being configured onto a multidrop line and the user does not want to
receive its own transmission. Although BISYNC usually uses a half-duplex protocol, the receiver
is not actually disabled during transmission.
10–11 — Reserved, should be cleared.
12–13 RPM Receiver parity mode. Selects the type of parity check that the receiver performs. RPM can be
modified on the fly and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled
but can be ignored.
00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is
set to ensure an odd number. An even sum indicates a transmission error.
01 Low parity. If the parity bit is not low, a parity error is reported.
10 Even parity. An even number must result from the calculation performed at both ends of the line.
11 High parity. If the parity bit is not high, a parity error is reported.
14–15 TPM Transmitter parity mode. Selects the type of parity the transmitter performs and can be modified on
the fly. TPM is ignored unless CRC = 11 (LRC).
00 Odd parity.
01 Force low parity (always send a zero in the parity bit position).
10 Even parity.
11 Force high parity (always send a one in the parity bit position).
26.12 SCC BISYNC Receive BD (RxBD)
The CP uses BDs to report on each buffer received. It closes the buffer, generates a maskable interrupt,
and starts receiving data into the next buffer after any of the following:
• A user-defined control character is received.
• An error is detected.
• A full receive buffer is detected.
• The
ENTER HUNT MODE
• The
CLOSE RX BD
Figure 26-6 shows the SCC BISYNC RxBD
.
0 1
Offset + 0 E —
Offset + 2
Offset + 4
Offset + 6
Freescale Semiconductor
Table 26-10. PSMR Field Descriptions (continued)
command is issued.
command is issued.
2 3 4 5 6
W I L F CM
Rx Data Buffer Pointer
Figure 26-6. SCC BISYNC RxBD
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
7 8 9 10 11
— DE — NO
Data Length
SCC BISYNC Mode
12 13 14 15
PR CR OV CD
26-11