Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 87

— Chapter 37, "Buffer Descriptors and Connection Tables,"
configuration of the buffer descriptors (BDs) and the transmit and receive connection tables
(TCTs and RCTs) used with ATM.
— Chapter 38, "ATM Parameter RAM,"
the four SCCs for serial ATM and the UTOPIA interface. The CP also uses parameter RAM to
store operational and temporary values used during SAR activities.
— Chapter 39, "ATM Controller,"
controller to support connection tables for both single- and multi-PHY interfaces, and the
commands provided to control ATM transmit and receive operations on a channel-by-channel
basis.
— Chapter 40, "ATM Pace Control,"
traffic parameters of each channel and defines the multiplex timing for all the channels.
— Chapter 41, "ATM Exceptions,"
an event register (SCCE or IDSR1) to provide an interrupt model for ATM operations.
— Chapter 42, "Interface Configuration,"
for ATM operations through both the UTOPIA and serial interfaces.
— Chapter 43, "UTOPIA Interface,"
operation, including the UTOPIA modes and the signals provided for UTOPIA support.
— Chapter 44, "AAL2 Implementation,"
• Part VII, "Fast Ethernet Controller (FEC),"
Ethernet. It consists of the following chapter:
— Chapter 45, "Fast Ethernet Controller (FEC),"
implemented on all MPC885 parts. It provides general descriptions of supported operations,
full descriptions of the supporting registers, and initialization information.
• Part VIII, "Integrated Security Engine (SEC Lite),"
security engine. It contains the following chapters:
— Chapter 46, "SEC Lite Overview,"
the features.
— Chapter 47, "SEC Lite Address Map,"
— Chapter 48, "SEC Lite Execution Units,"
unit (DEU), the Advanced Encryption Standard execution unit (AESU), and the message digest
execution unit (MDEU).
— Chapter 49, "SEC Lite Descriptors,"
the security operations.
— Chapter 50, "SEC Lite Crypto-Channel,"
associated with one of more execution units.
— Chapter 51, "SEC Lite Controller,"
SEC Lite to oversee the operations of the execution units (EUs), the interface to the host
processor, and the management of the crypto-channel.
Freescale Semiconductor
describes how the parameter RAM is used to configure
describes the address mapping mechanisms of the ATM
describes how the ATM pace control unit (APC) processes
describes how the circular ATM interrupt queue operates with
describes the programming of registers and parameters
describes the single- and multi-classic SAR MPHY ATM
describes the implementation of AAL2.
describes the MPC885 support for 10/100 base-T
gives a high-level description of the MPC885 SEC Lite and
describes the memory used by the SEC Lite.
describes the descriptors used to take SEC Lite through
describes the responsibility of the controller within the
MPC885 PowerQUICC Family Reference Manual, Rev. 2
describes the structure and
describes the Fast Ethernet Controller, which is
describes the MPC885 implementation of the
describes the Data Encryption Standard execution
describes how the crypto-channel manages data
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