Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 225

Table 7-7. Data Cache Control and Status Register—DC_CST (continued)
Bits Name
11 CCER2 Data cache error type 2. This bit indicates one of two possible errors—either a bus error during
DC_CST load & load cache block or flush cache block command or there is no unlocked way
available for a DC_CST load-and-lock cache block or flush cache block command.
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected. Reading
this bit clears it.
12–31 — Reserved
The DC_ADR register, shown in
0
Field
Reset
R/W
SPR
Table 7-8 describes the bits of the DC_ADR register.
Bits Name
0–31 ADR Data cache command address. When programming the DC_CST load-and-lock cache block,
unlock cache block, and flush cache block commands, DC_ADR contains the physical address
of the desired cache block element in external memory. When reading the data, tags, and status
contained within the data cache, DC_ADR is used to qualify what is to be read according to
Table 7-8. See
information.
The DC_DAT register, shown in
0
Field
Reset
R/W
SPR
Freescale Semiconductor
Figure 7-7, has an SPR encoding of 569.
Figure 7-7. Data Cache Address Register (DC_ADR)
Table 7-8. Data Cache Address Register—DC_ADR
Section 7.3.2.1, "Reading Data Cache Tags and Copyback Buffer,"
Figure 7-8, has an SPR encoding of 570.
Figure 7-8. Data Cache Data Port Register (DC_DAT)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
ADR
—
R/W
569
Description
DAT
—
R/W
570
Instruction and Data Caches
31
for more
31
7-13