Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 457

15.4.6 Memory Data Register (MDR)
The memory data register (MDR) contains data written to or read from the RAM array for UPM
commands. MDR must be set up before issuing a
WRITE
0
Field
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
This register is not affected by HRESET or SRESET.
Bits Name
0–31 MD Memory data. Contains the RAM array word.
15.4.7 Memory Address Register (MAR)
The memory address register contains an address to be driven on the external bus in the case of a
command issued to the MCR.
0
Field
Reset
R/w
Addr
16
Field
Reset
R/W
Addr
Freescale Semiconductor
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x17C
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x17E
Figure 15-12. Memory Data Register (MDR)
Table 15-8. MDR Field Descriptions
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x164
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x166
Figure 15-13. Memory Address Register (MAR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
command to the MCR.
WRITE
MD
R/W
MD
R/W
Table 15-8 describes MDR.
Description
MA
R/W
MA
R/W
Memory Controller
or
READ
15
31
RUN
15
31
15-17