Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 496

Memory Controller
generates control signals to the slave device. When AS is synchronized, the memory controller compares
the address with each of its defined valid banks; if a match is found, control signals to the slave are
generated and TA is supplied to the external master. All control signals to the memory device and TA are
negated with the negation of AS. If AEME = 0, the memory controller is bypassed and the external
asynchronous master must provide control signals to the slave. In this mode, the MPC885's AS signal
cannot be used as an input. See
15.8.3 Special Case: Address Type Signals for External
Masters
The AT signals are not sampled on the external bus for external master accesses. When external masters
access slaves on the bus, the internal AT[0:2] signals reaching the memory controller are forced to '100'.
The user should ensure this access matches the BRx[AT]. It is masked by ORx[ATM].
15.8.4 UPM Features Supporting External Masters
The following sections provide information about the UPM features that support external masters.
15.8.4.1 Address Incrementing for External Synchronous Bursting
Masters
BADDR[28:30] should be used to generate addresses to memory devices for burst accesses. They
duplicate the value of A[28:30] when an internal master initiates an external bus transaction. When an
external master initiates an external bus transaction, they reflect the value of A[28:30] on the first clock
cycle of the memory access; these signals are latched by the memory controller and on subsequent clock
cycles, BADDR[28:30] increments as programmed in the UPM.
15.8.4.2 Handshake Mechanism for Asynchronous External Masters
A wait mechanism in the UPM supports handshaking for external asynchronous masters. This is provided
with an AS input signal and the WAEN bit in the UPM RAM words. See
Mechanism (WAEN)."
15.8.4.3 Special Signal for External Address Multiplexer Control
If external masters exist in the system with the MPC885, address multiplexing (for DRAM for example)
must be implemented in external logic. To control this external multiplexer, special features have been
added to GPL5. See Section 15.6.4.4, "General-Purpose Signals (GxTx, G0x)."
15-56
Figure 15-48.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 15.6.4.11, "The Wait
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