Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 556

Communications Processor Module and CPM Timers
17.1 Features
Figure 17-1 shows a block diagram of the CPM.
Interrupt Controller
Parallel I/O Ports
4 Baud Rate Generators
USB
The following lists the CPM's main features:
• Communications processor (CP)
— Dual-port RAM
— Internal ROM
— DMA control for all communications channels
— Two independent DMA channels for memory-to-memory transfers or interfacing external
peripherals
— RISC timer tables
• Three full-duplex serial communications controllers (SCCs) that support the following:
— UART protocol (asynchronous or synchronous)
— HDLC protocol
— AppleTalk protocol
17-2
4 Timers
Peripheral Bus
SCC2 SCC3 SCC4
Serial Interface and Time-Slot Assigner
Figure 17-1. CPM Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
U-Bus
Bus Interface
Internal Bus
Communications Processor
Dual-Port
RAM
SMC1 SMC2
SDMA
ROM
SPI I 2 C
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