Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 170

MPC8xx Core Register Set
4.2 Register Initialization at Reset
This section describes how basic registers are set under reset conditions, other register settings are
described in Chapter 7, "Instruction and Data Caches,"
A system reset interrupt occurs when a nonmaskable interrupt is generated either by the software watchdog
timer or the assertion of IRQ0. The only registers affected by the system reset interrupt are MSR, SRR0,
and SRR1; no other reset activity occurs.
values for these registers after system reset.
When a hard or soft reset occurs, registers are set in the same way, as follows:
• SRR0, SRR1—Set to an undefined value
• MSR[IP]—Programmable through the IIP bit in the hard reset configuration word
• MSR[ME]—Cleared
• ICTRL—Cleared
• LCTRL1—Cleared
• LCTRL2—Cleared
• COUNTA[16–31]—Cleared
• COUNTB[16–31]—Cleared
• ICR—Cleared (no exception occurred)
• DER[2,14,28–31]—Set (all debug-specific exceptions cause debug mode entry)
Reset values for memory-mapped registers are provided with individual register descriptions throughout
this manual.
4-12
Section 6.1.2.1, "System Reset Interrupt (0x00100),"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
and Chapter 8, "Memory Management Unit."
describes
Freescale Semiconductor