Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 733

0 1
Offset + 0 E —
Offset + 2
Offset + 4
Offset + 6
Table 25-10 describes the SCC asynchronous HDLC RxBD status and control fields.
Bits Name
0 E Empty
0 The buffer is full or stops receiving because of an error. The core can read or update any fields
of this RxBD. The CPM cannot reuse this BD while E = 0.
1 The buffer is not full. The CP controls the BD and buffer. The core should not update the BD.
1 — Reserved, should be cleared.
2 W Wrap (last BD in table)
0 Not the last BD in the table
1 Last BD in the table. After this buffer is used, the CPM receives incoming data using the BD
pointed to by RBASE. The number of RxBDs in a table is determined by the W bit.
3 I Interrupt
0 SCCE[RXB] is not set after this buffer is used. SCCE[RXF] is unaffected.
1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the asynchronous HDLC
controller.
4 L Last in frame
0 Not the last buffer in a frame
1 Set by SCC when a buffer is the last in a frame which happens when a closing flag or error is
received. If an error occurs, one or more of the BRK, CD, OV, BOF, CR, and AB bits are set.
The SCC updates RxBD[Data Length].
5 F First in frame. Set by the SCC when this buffer is the first in a frame.
0 Not the first buffer in a frame
1 First buffer in a frame
6 CM Continuous mode
0 Normal operation
1 The CP does not clear E after the BD is closed allowing a buffer to be overwritten when the CP
next accesses the BD. However, E is cleared if an error other than CRC occurs during
reception, regardless of CM.
7 — Reserved, should be cleared.
8 BRK Break character received. Set when a frame is closed because a break character is received.
9 BOF Beginning of frame. Set when a frame is closed because a BOF character is received instead of
the expected EOF.
10–11 — Reserved, should be cleared.
12 AB Rx abort sequence. Set when an abort sequence or framing error terminates a frame.
Freescale Semiconductor
2 3 4 5 6
W I L F CM
Rx Buffer Pointer
Figure 25-7. SCC Asynchronous HDLC RxBDs
Table 25-10. Asynchronous HDLC RxBD Status
and Control Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SCC Asynchronous HDLC Mode and IrDA
7 8 9 10 11
— BRK BOF —
Data Length
Description
12 13 14 15
AB CR OV CD
25-11