Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 44

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53.1.4 Program Trace Special Cases..................................................................................... 53-4
53.1.4.1 Queue Flush Information Special Case ................................................................. 53-4
53.1.4.2 Program Trace When In Debug Mode................................................................... 53-4
53.1.4.3 Sequential Instructions Marked as Indirect Branch............................................... 53-5
53.1.5 Reconstructing Program Trace .................................................................................. 53-5
53.1.5.1 Back Trace ............................................................................................................. 53-5
53.1.5.2 Window Trace........................................................................................................ 53-5
53.1.5.2.1 Synchronizing the Trace Window to Internal Core Events ............................... 53-5
53.1.5.3 Detecting the Trace Window Start Address........................................................... 53-6
53.1.5.4 Detecting the Assertion/Negation of VSYNC ....................................................... 53-7
53.1.5.5 Detecting the Trace Window End Address............................................................ 53-7
53.1.5.6 Efficient Trace Information Capture...................................................................... 53-7
53.2 Watchpoints and Breakpoints Support........................................................................... 53-7
53.2.1 Key Features .............................................................................................................. 53-8
53.2.2 Internal Watchpoints and Breakpoints Logic........................................................... 53-10
53.2.3 Functional Description............................................................................................. 53-10
53.2.3.1 Instruction Support Detailed Description ............................................................ 53-10
53.2.3.2 Load/Store Support Detailed Description............................................................ 53-11
53.2.3.3 The Counters........................................................................................................ 53-13
53.2.3.4 Trap Enable Programming................................................................................... 53-14
53.2.4 Operation Details ..................................................................................................... 53-14
53.2.4.1 Restrictions .......................................................................................................... 53-14
53.2.4.2 Byte and Half Word Working Modes .................................................................. 53-14
53.2.4.2.1 Examples ......................................................................................................... 53-14
53.2.4.3 Context Dependent Filter..................................................................................... 53-16
53.2.4.4 Ignore First Match ............................................................................................... 53-16
53.2.4.5 Generating Six Compare Types ........................................................................... 53-16
53.2.5 Load/Store Breakpoint Example.............................................................................. 53-17
53.3 Development System Interface.................................................................................... 53-17
53.3.1 Debug Mode Operation ........................................................................................... 53-19
53.3.1.1 Debug Mode Enable vs. Debug Mode Disable ................................................... 53-20
53.3.1.2 Entering Debug Mode.......................................................................................... 53-21
53.3.1.3 Debug Mode Indication ....................................................................................... 53-22
53.3.1.4 Checkstop State and Debug Mode....................................................................... 53-22
53.3.1.5 Saving Machine State when Entering Debug Mode............................................ 53-23
53.3.1.6 Running in Debug Mode ..................................................................................... 53-23
53.3.1.7 Exiting Debug Mode............................................................................................ 53-23
53.3.2 Development Port Communication ......................................................................... 53-24
53.3.2.1 Development Port Pins ........................................................................................ 53-24
53.3.2.1.1 Development Serial Clock (DSCK) ................................................................ 53-24
53.3.2.1.2 Development Serial Data In (DSDI) ............................................................... 53-24
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Contents
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor