Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 589

19.1.2 U-Bus Arbitration and the SDMA Channels
The 4 physical SDMA channels, I-cache, D-cache, and SIU all contend for the U-bus as internal masters
with their relative priorities determined by an arbitration ID. The SDMA channels, I-cache, D-cache, and
SIU internal masters have fixed arbitration IDs; see
(SDCR)." All 22 virtual SDMA channels share the same arbitration ID, and thus have the same priority
relative to the other internal masters. See
Arbitration Level
7 (highest priority)
6
5
4
3
2
1
0
Notes: DRAM refresh normally has a U-bus arbitration level of 0 (losing ties to the G2 core). However, if four refresh
periods expire without servicing, the arbitration level is promoted to 7.
An external request loses ties to an internal request or DRAM refresh request with the same arbitration ID. For
example, if SIUMCR[EARP] is 4, the external master has priority over the I-cache but not over the D-cache.
Once an SDMA channel obtains the external system bus, it remains master for the whole transaction—a
byte, half-word, word or burst transfer—before relinquishing the bus. This feature, in combination with
the zero-clock arbitration overhead provided by the U-bus, increases bus efficiency and lowers latency.
To minimize the latency associated with slower, character-oriented protocols, an SDMA writes each
character to memory as it arrives without waiting for the next character, and always reads using 16-bit
half-word transfers. A transfer may take multiple bus cycles if the memory provides a less than 32-bit port
size. An SDMA uses back-to-back bus cycles for the entire transfer—4-word bursts, 32-bit reads, and 8-,
16-, or 32-bit writes—before relinquishing the bus. For example, an SDMA channel reading a 32-bit word
from a 16-bit memory takes two consecutive bus cycles.
An SDMA steals cycles with no arbitration overhead unless an external device is bus master.
shows an SDMA stealing a cycle from an internal bus master.
Freescale Semiconductor
Section 19.2.1, "SDMA Configuration Register
Table 19-1.
Table 19-1. U-Bus Arbitration IDs
—
SDMA
—
D-cache
I-cache
—
—
G2 core
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SDMA Channels and IDMA Emulation
Unit
Figure 19-2
19-3