Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 37

Paragraph
Number
41.1 ATM Event Registers..................................................................................................... 41-2
41.1.1 UTOPIA Event Register (IDSR1) ............................................................................. 41-2
41.1.2 Serial ATM Event Register (SCCE) .......................................................................... 41-3
41.2 Interrupt Queue Entry .................................................................................................... 41-4
41.3 Interrupt Queue Mask (IMASK).................................................................................... 41-6
42.1 General ATM Registers ................................................................................................. 42-1
42.1.1 Port D Pin Assignment Register (PDPAR)................................................................ 42-1
42.1.2 APC Timer (CPM Timer 4) ....................................................................................... 42-2
42.1.3 RISC Timer ................................................................................................................ 42-2
42.2 UTOPIA Mode Registers............................................................................................... 42-2
42.2.1 System Clock Control Register (SCCR).................................................................... 42-2
42.2.2 Port B—MasterTxClav/Slave RxClav and PHY Address Signals ............................ 42-3
42.2.3 Port C—MasterRxClav/Slave TxClav Signal............................................................ 42-4
42.2.4 Port D—UTOPIA Data and Control Signals ............................................................. 42-5
42.2.5 PCMCIA Port A Signal Multiplexing ....................................................................... 42-6
42.2.6 RISC Controller Configuration Register (RCCR) ..................................................... 42-6
42.2.7 UTOPIA Mode Initialization ..................................................................................... 42-6
42.3 Serial ATM Configuration ............................................................................................. 42-7
42.3.1 RISC Controller Configuration Register (RCCR) ..................................................... 42-7
42.3.2 SCC Configuration for Serial ATM ........................................................................... 42-7
42.3.2.1 General SCC Mode Register (GSMR) .................................................................. 42-7
42.3.2.1.1 Bit-Aligned Cell Delineation............................................................................. 42-7
42.3.2.2 Serial ATM Mode Register (PSMR)...................................................................... 42-8
42.3.3 SI Configuration for Serial ATM ............................................................................... 42-8
43.1 UTOPIA Features .......................................................................................................... 43-1
43.2 UTOPIA Mode Register (UTMODE) ........................................................................... 43-1
43.3 UTOPIA Operation........................................................................................................ 43-5
43.3.1 UTOPIA Split Bus ..................................................................................................... 43-6
43.3.2 UTOPIA Muxed Bus (Master Operation Only) ........................................................ 43-6
Freescale Semiconductor
Contents
Title
Chapter 41
ATM Exceptions
Chapter 42
Interface Configuration
Chapter 43
UTOPIA Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
xxxvii