Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 464

Memory Controller
Clock
Address
TS
TA
CS
R/W
WE
OE
Data
Figure 15-22. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1)
When TRLX and CSNT are set in a write-memory access, the strobe line, WE is negated one clock earlier
than in the normal case. If ACS ≠ 0, CS is also negated one clock earlier, as shown in
Figure 15-24. When a bank is selected to operate with external transfer acknowledge (SETA and
TRLX = 1), the memory controller does not support external devices that provide TA to complete the
transfer with zero wait states. The minimum access duration in this case is 3 clock cycles.
15-24
MPC885 PowerQUICC Family Reference Manual, Rev. 2
ACS = 10
ACS = 11
Figure 15-23 and
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