Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 182

Powerquicc family

Table of Contents

MPC885 Instruction Set

Load Word and Zero

Load Word and Zero Indexed

Load Word and Zero with Update

Load Word and Zero with Update Indexed

Integer Store Instructions

For integer store instructions, the contents of rS are stored into the byte, half word, word, or double word

in memory addressed by the effective address (EA). Many store instructions have an update form, in which

rA is updated with the EA. For these forms, the following rules apply:

If rA ≠ 0, the EA is placed into rA.

If rS = rA, the contents of rS are copied to the target memory element, then the generated EA is

placed into rA (rS).

The MPC885 defines store with update instructions with rA = 0 and integer store instructions with the CR

update option enabled (Rc[31] = 1) to be invalid forms.

Store Byte Indexed

Store Byte with Update

Store Byte with Update Indexed

Store Half Word

Store Half Word Indexed

Store Half Word with Update

Store Half Word with Update Indexed

Store Word Indexed

Store Word with Update

Store Word with Update Indexed

Integer Load and Store with Byte-Reverse Instructions

describes integer load and store with byte-reverse instructions. When used in a system operating

with the default big-endian byte order, these instructions have the effect of loading and storing data in

little-endian order. Likewise, when used in a system operating with little-endian byte order, these

instructions have the effect of loading and storing data in big-endian order. For more information about

Table 5-7. Integer Load Instructions (continued)

Table 5-8. Integer Store Instructions

MPC885 PowerQUICC Family Reference Manual, Rev. 2

lists integer store instructions for the

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