Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 761

Powerquicc family

Table of Contents

Connecting the MPC885 to Ethernet

The basic interface to the external EEST chip consists of the following ethernet signals:

Receive clock (RCLK)—a CLKx signal routed through the bank of clocks on the MPC885

Transmit clock (TCLK)—a CLKx signal routed through the bank of clocks on the MPC885. Note

that RCLK and TCLK should not be connected to the same CLKx since the EEST provides

separate transmit and receive clock signals.

Transmit data (TXD)—the MPC885 TXD signal

Receive data (RXD)—the MPC885 RXD signal

The following signals take on different functionality when the SCC is in ethernet mode:

Transmit enable (TENA)—RTS becomes TENA. The polarity of TENA is active high, whereas the

polarity of RTS is active low.

Receive enable (RENA)—CD becomes RENA

Collision (CLSN)—CTS becomes CLSN. The carrier sense signal is referenced in ethernet

descriptions because it indicates when the LAN is in use. Carrier sense is defined as the logical OR

of RENA and CLSN.

shows the basic components and signals required to make an ethernet connection between the

MPC885 and EEST.

Parallel I/O

Note: Short Tx frames are padded automatically by the MPC885

The EEST has similar names for its connection to the above seven MPC885 signals. The EEST also

provides a loop-back input so the MPC885 can perform external loop-back testing, which can be

controlled by any available MPC885 parallel I/O signal. The passive components needed to connect to

Freescale Semiconductor

Stored in Transmit Buffer

Figure 27-3. Connecting the MPC885 to Ethernet

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Stored in Receive Buffer

46–1500 Bytes

SCC Ethernet Mode