Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 922

Parallel I/O Ports
0
Field
Reset
R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–7, 13, 15 — Reserved, should be cleared.
8–12, 14 OD n Tells how the corresponding port A signal is interpreted.
0 The signal is actively driven as an output.
1 The signal is an open-drain driver. Outputs are actively driven low. Otherwise, it is
34.2.1.2 Port A Data Register (PADAT)
Reading the port A data (PADAT) register returns the value of the signal, regardless of whether the signal
is an input or output. Comparing written data with the data on the signal can detect output conflicts. A write
to a PADAT bit is latched; if the bit is configured as an output, the value latched for that bit is driven onto
its respective signal. PADAT can be read or written at any time, is not initialized, and is undefined at reset.
0 1
Field D0 D1
Reset 0 0
R/W R/W R/W R/W
Addr
This register is not affected by HRESET or SRESET.
Bits Name
0–15 D n Contains the data on the corresponding signal
34.2.1.3 Port A Data Direction Register (PADIR)
Port A data direction register (PADIR) bits configure port A signals as general-purpose inputs or outputs.
If a signal is not programmed for general-purpose I/O, PADIR selects the peripheral function to be
performed.
34-4
7
—
Figure 34-1. Port A Open-Drain Register (PAODR)
Table 34-2. PAODR Bit Descriptions
three-stated.
2 3 4 5 6
D2 D3 D4 D5 D6
0 0 0 0 0
R/W R/W R/W R/W
Figure 34-2. Port A Data Register (PADAT)
Table 34-3. PADAT Bit Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
8 9 10 11
OD8 OD9 OD10 OD11 OD12
0
R/W
0x954
Table 34-2
Description
7 8 9 10 11
D7 D8 D9 D10 D11
0 0 0 0 0
R/W R/W R/W R/W R/W
0x956
Table 34-3 describes PADAT bits.
Description
12 13 14 15
— OD14 —
describes PAODR bits.
12 13 14 15
D12 D13 D14 D15
0 0 0 0
R/W R/W R/W R/W
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