Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 59

Figure
Number
30-6 SPI Transfer Format with SPMODE[CP] = 1....................................................................... 30-7
30-7 SPI Event/Mask Registers (SPIE/SPIM) .............................................................................. 30-9
30-8 SPI Command Register (SPCOM)........................................................................................ 30-9
30-9 Receive/Transmit Function Code Registers (RFCR/TFCR)............................................... 30-11
30-10 SPI Memory Structure......................................................................................................... 30-12
30-11 SPI Receive BD (RxBD)..................................................................................................... 30-13
30-12 SPI Transmit BD (TxBD) ................................................................................................... 30-14
31-1 USB Interface........................................................................................................................ 31-3
31-2 USB Controller Block Diagram ........................................................................................... 31-5
31-3 USB Controller Operating Modes......................................................................................... 31-6
31-4 USB Controller (Host Mode)................................................................................................ 31-8
31-5 USB Controller Operating Modes......................................................................................... 31-9
31-6 SOF Generation................................................................................................................... 31-11
31-7 USB Parameter RAM Memory Map .................................................................................. 31-12
31-8 Endpoint Pointer Registers (EPxPTR) ................................................................................ 31-12
31-9 Frame Number (FRAME_N) in Function mode................................................................. 31-14
31-10 Frame Number (FRAME_N) in HOST mode..................................................................... 31-15
31-11 USB Function Code Registers (RFCR and TFCR)............................................................. 31-15
31-12 USB Mode Register (USMOD) .......................................................................................... 31-16
31-13 USB Slave Address Register (USADR) ............................................................................. 31-17
31-14 USB Endpoint Registers (USEP0–USEP3) ........................................................................ 31-18
31-15 USB Command Register (USCOM) ................................................................................... 31-19
31-16 USB Event Register (USBER)............................................................................................ 31-20
31-17 USB Status Register (USBS) .............................................................................................. 31-21
31-18 USB Memory Structure....................................................................................................... 31-22
31-19 USB Receive Buffer Descriptor (RxBD),........................................................................... 31-23
31-20 USB Transmit Buffer Descriptor (TxBD),.......................................................................... 31-25
31-21 USB Transmit Buffer Descriptor (TxBD),.......................................................................... 31-26
32-1 I2C Controller Block Diagram.............................................................................................. 32-1
32-2 I2C Master/Slave General Configuration ............................................................................. 32-2
32-3 I2C Transfer Timing.............................................................................................................. 32-3
32-4 I2C Master Write Timing...................................................................................................... 32-3
32-5 I2C Master Read Timing....................................................................................................... 32-4
2
32-6 I C Mode Register (I2MOD) ................................................................................................ 32-6
2
32-7 I C Address Register (I2ADD) ............................................................................................. 32-7
32-8 I2C Baud Rate Generator Register (I2BRG) ........................................................................ 32-7
2
32-9 I C Event/Mask Registers (I2CER/I2CMR)......................................................................... 32-8
2
32-10 I C Command Register (I2COM) ......................................................................................... 32-8
2
32-11 I C Function Code Registers (RFCR/TFCR)...................................................................... 32-10
2
32-12 I C Memory Structure......................................................................................................... 32-11
2
32-13 I C Receive Buffer Descriptor (RxBD) .............................................................................. 32-12
Freescale Semiconductor
Figures
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
lix