Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 923

0 1 2
Field DR0 DR1 DR2
Reset 0 0 0
R/W R/W R/W R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–15 DR n Port A data direction. Configures port A signals as inputs or outputs when functioning as
general-purpose I/O; otherwise, used to select the peripheral function.
0 Select the signal for general-purpose input, or select peripheral function 0.
1 Select the signal for general-purpose output, or select peripheral function 1.
34.2.1.4 Port A Pin Assignment Register (PAPAR)
The port A pin assignment register (PAPAR) configures signals as general-purpose I/O or dedicated for
use with a peripheral.
0 1 2
Field DD0 DD1 DD2
Reset 0 0 0
R/W R/W R/W R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–15 DD n Configures a signal for general-purpose I/O or for dedicated peripheral function
0 General-purpose I/O. The peripheral functions of the signal are not used.
1 Dedicated peripheral function. The signal is used by the internal module. The on-chip
peripheral function to which it is dedicated can be determined by other bits.
34.2.2 Port A Configuration Examples
This section describes the configuration for several PA signals, which are as follows:
• PA15 can be configured as a general-purpose I/O signal but not as an open-drain signal. It can also
be USBRXD for the USB. If it is configured as a general-purpose I/O signal, the RXD1 input is
internally grounded.
Freescale Semiconductor
3 4 5 6
DR3 DR4 DR5 DR6
0 0 0 0
R/W R/W R/W R/W
Figure 34-3. Port A Data Direction Register (PADIR)
Table 34-4. PADIR Bit Descriptions
3 4 5 6
DD3 DD4 DD5 DD6
0 0 0 0
R/W R/W R/W R/W
Figure 34-4. Port A Pin Assignment Register (PAPAR)
Table 34-5. PAPAR Bit Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10 11
DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15
0 0 0 0
R/W R/W R/W R/W R/W
0x950
Table 34-4
Description
7 8 9 10 11
DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
0 0 0 0
R/W R/W R/W R/W R/W
0x952
Table 34-5
Description
Parallel I/O Ports
12 13 14 15
0 0 0 0 0
R/W R/W R/W R/W
describes PADIR bits.
12 13 14 15
0 0 0 0 0
R/W R/W R/W R/W
describes PAPAR bits.
34-5