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Freescale Semiconductor PowerQUICC MPC885 Reference Manual

Freescale Semiconductor PowerQUICC MPC885 Reference Manual

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MPC885

PowerQUICC™ Family

Reference Manual

Supports:

MPC885

MPC880

MPC875

MPC870

MPC885RM

Rev. 2, 04/2006

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Summary of Contents for Freescale Semiconductor PowerQUICC MPC885

Page 1 MPC885 PowerQUICC™ Family Reference Manual Supports: MPC885 MPC880 MPC875 MPC870 MPC885RM Rev. 2, 04/2006...
Page 2 Freescale Semiconductor product For Literature Requests Only: could create a situation where personal injury or death may occur. Should Buyer...
Page 3 Part I—Overview MPC885 Overview Memory Map Part II—MPC8xx Microprocessor Module The MPC8xx Core MPC8xx Core Register Set MPC885 Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III—Configuration and Reset System Interface Unit Reset Part IV—Hardware Interface External Signals External Bus Interface Clocks and Power Control...
Page 4 Part I—Overview MPC885 Overview Memory Map Part II—MPC8xx Microprocessor Module The MPC8xx Core MPC8xx Core Register Set MPC885 Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III—Configuration and Reset System Interface Unit Reset Part IV—Hardware Interface External Signals External Bus Interface Clocks and Power Control...
Page 5 Part VI—Asynchronous Transfer Mode (ATM) ATM Overview Buffer Descriptors and Connection Tables ATM Parameter RAM ATM Controller ATM Pace Control ATM Exceptions Interface Configuration UTOPIA Interface AAL2 Implementation Part VII—Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) Part VIII—Integrated Security Engine (SEC Lite) VIII SEC Lite Overview SEC Lite Address Map...
Page 6 Part VI—Asynchronous Transfer Mode (ATM) ATM Overview Buffer Descriptors and Connection Tables ATM Parameter RAM ATM Controller ATM Pace Control ATM Exceptions Interface Configuration UTOPIA Interface AAL2 Implementation Part VII—Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) VIII Part VIII—Integrated Security Engine (SEC Lite) SEC Lite Overview SEC Lite Address Map SEC Lite Execution Units...
Page 7 Part II MPC8xx Microprocessor Module Chapter 3 The MPC8xx Core The MPC885 Core as a PowerPC Implementation ............3-1 PowerPC Architecture Overview..................3-2 3.2.1 Levels of the PowerPC Architecture ................3-3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 8 PowerPC Supervisor-Level Register Bit Assignments..........4-6 4.1.2.3.1 Machine State Register (MSR)................4-6 4.1.2.3.2 Processor Version Register .................. 4-8 4.1.3 MPC885-Specific SPRs....................4-9 4.1.3.1 Accessing SPRs ..................... 4-11 Register Initialization at Reset ..................4-12 MPC885 PowerQUICC Family Reference Manual, Rev. 2 viii Freescale Semiconductor...
Page 9 Branch Instructions.................... 5-15 5.2.4.3.3 Condition Register Logical Instructions............5-15 5.2.4.4 Trap Instructions ....................5-15 5.2.4.5 Processor Control Instructions................5-16 5.2.4.5.1 Move to/from Condition Register Instructions..........5-16 5.2.4.6 Memory Synchronization Instructions—UISA ............. 5-16 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 10 Instruction TLB Error Exception (0x01300) ............6-13 6.1.3.5 Data TLB Error Exception (0x014000) ..............6-14 6.1.3.6 Debug Exceptions (0x01C00–0x01F00) ............... 6-15 6.1.4 Implementing the Precise Exception Model.............. 6-16 6.1.5 Recoverability After an Exception ................6-16 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 11 Instruction Cache Miss ....................7-21 7.5.3 Instruction Fetching on a Predicted Path ..............7-21 7.5.4 Fetching Instructions from Caching-Inhibited Regions..........7-22 7.5.5 Updating Code and Memory Region Attributes ............7-22 Data Cache Operation ....................7-22 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 12 IMMU Real Page Number Register (MI_RPN) ............8-19 8.8.7 DMMU Real Page Number Register (MD_RPN) ............. 8-20 8.8.8 MMU Tablewalk Base Register (M_TWB)............... 8-22 8.8.9 MMU Current Address Space ID Register (M_CASID)........... 8-22 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 13 String Instruction Latency ................... 9-8 9.2.3 Accessing Off-Core SPRs.................... 9-8 Part III Configuration and Reset Chapter 10 System Interface Unit 10.1 Features .......................... 10-1 10.2 System Configuration and Protection ................10-2 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xiii...
Page 14 Freeze Operation...................... 10-28 Chapter 11 Reset 11.1 Types of Reset........................ 11-1 11.1.1 Power-On Reset ......................11-2 11.1.2 External Hard Reset ....................11-2 11.1.3 Internal Hard Reset ....................11-2 11.1.3.1 Software Watchdog Reset..................11-3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 15 Reset Configuration ....................12-42 12.6.1.1 Bus Control Signals and Interrupts..............12-42 12.6.2 JTAG and Debug Ports .................... 12-43 12.6.3 Unused Inputs ......................12-43 12.6.4 Unused Outputs......................12-43 12.7 Signal States During Reset................... 12-44 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 16 13.4.8.4 Termination Signals Protocol ................13-33 13.4.9 Memory Reservation....................13-35 13.4.9.1 Cancel Reservation (CR) ..................13-35 13.4.9.2 Kill Reservation (KR)..................13-36 13.4.10 Bus Exception Control Cycles................. 13-37 13.4.10.1 RETRY ........................ 13-38 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 17 15.3.1 Address Space Programming..................15-7 15.3.2 Register Programming Order..................15-7 15.3.3 Memory Bank Write Protection................. 15-7 15.3.4 Address Type Protection.................... 15-7 15.3.5 8-, 16-, and 32-Bit Port Size Configuration............... 15-7 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xvii...
Page 18 Loop Control (LOOP)..................15-45 15.6.4.6 Exception Pattern Entry (EXEN)................. 15-46 15.6.4.7 Address Multiplexing (AMX) ................15-46 15.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3) ......15-51 15.6.4.9 Disable Timer Mechanism (TODT)..............15-52 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xviii Freescale Semiconductor...
Page 19 Reset and Three-State Control ................... 16-7 16.3.6 DMA .......................... 16-7 16.4 Programming Model ...................... 16-8 16.4.1 PCMCIA Interface Input Pins Register (PIPR) ............16-8 16.4.2 PCMCIA Interface Status Changed Register (PSCR) ..........16-10 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 20 18.4 CP Microcode Revision Number ................... 18-4 18.5 CPM Configuration Register (CPMCFG) ..............18-4 18.6 CP Register Set and CP Commands ................18-5 18.6.1 RISC Controller Configuration Register (RCCR) ............. 18-5 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 21 DMA Channel Mode Registers (DCMR) .............. 19-8 19.3.3.2 IDMA Status Registers (IDSR1 and IDSR2) ............19-9 19.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2)............19-9 19.3.4 IDMA Buffer Descriptors (BD)................. 19-9 19.3.4.1 Function Code Registers—SFCR and DFCR............19-12 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 22 SI Command Register (SICMR)................20-24 20.2.4.5 SI Status Register (SISTR) .................. 20-24 20.2.4.6 SI RAM Pointer Register (SIRP)................. 20-25 20.2.5 IDL Bus Implementation ..................20-27 20.2.5.1 ISDN Terminal Adaptor Application..............20-27 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxii Freescale Semiconductor...
Page 23 Reset Sequence for an SCC Transmitter.............. 21-26 21.4.7.3 General Reconfiguration Sequence for an SCC Receiver ........21-26 21.4.7.4 Reset Sequence for an SCC Receiver..............21-26 21.4.7.5 Switching Protocols ..................... 21-26 21.4.8 Saving Power ......................21-26 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxiii...
Page 24 SCC HDLC Receive Buffer Descriptor (RxBD) ............23-8 23.10 SCC HDLC Transmit Buffer Descriptor (TxBD)............23-11 23.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ......... 23-12 23.12 SCC HDLC Status Register (SCCS)................23-14 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxiv Freescale Semiconductor...
Page 25 Configuring GSMR and DSR for Asynchronous HDLC ..........25-6 25.9.1 General SCC Mode Register (GSMR)............... 25-6 25.9.2 Data Synchronization Register (DSR)............... 25-6 25.10 Programming the Asynchronous HDLC Controller ............25-6 25.11 Asynchronous HDLC Commands ................. 25-6 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 26 Ethernet on the MPC885....................27-2 27.2 Features .......................... 27-3 27.3 Learning Ethernet on the MPC885 ................27-4 27.4 Connecting the MPC885 to Ethernet ................27-5 27.5 SCC Ethernet Channel Frame Transmission ..............27-6 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxvi Freescale Semiconductor...
Page 27 Transparent Mode and the PSMR.................. 28-7 28.9 SCC Transparent Receive Buffer Descriptor (RxBD) ........... 28-8 28.10 SCC Transparent Transmit Buffer Descriptor (TxBD)..........28-9 28.11 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)......28-10 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxvii...
Page 28 29.4.3 SMC Transparent Channel Transmission Process ........... 29-21 29.4.4 SMC Transparent Channel Reception Process ............29-21 29.4.5 Using SMSYN for Synchronization ................ 29-22 29.4.6 Using TSA for Synchronization ................29-23 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxviii Freescale Semiconductor...
Page 29 SPI Command Register (SPCOM) ................30-9 30.5 SPI Parameter RAM ....................30-10 30.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)........30-11 30.6 SPI Commands ......................30-12 30.7 The SPI Buffer Descriptor (BD) Table ................ 30-12 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxix...
Page 30 USB Receive Buffer Descriptor (RxBD) for Host and Function ......31-23 31.12.2 USB Transmit Buffer Descriptor (TxBD) for Function........... 31-25 31.12.3 USB Transmit Buffer Descriptor (TxBD) for Host ..........31-26 31.13 USB CP Commands..................... 31-28 31.13.1 STOP Tx Command (USBCMD=001)..............31-28 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 31 The PIP Parameter RAM ....................33-3 33.3.1 PIP Transmitter Parameter RAM................33-3 33.3.1.1 PIP Function Code Register (PFCR) ..............33-4 33.3.1.2 Status Mask Register (SMASK) ................33-4 33.3.2 PIP Receiver Parameter RAM ................... 33-5 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxxi...
Page 32 Port B Open-Drain Register (PBODR)..............34-9 34.3.1.2 Port B Data Register (PBDAT)................34-9 34.3.1.3 Port B Data Direction Register (PBDIR)............. 34-10 34.3.1.4 Port B Pin Assignment Register (PBPAR) ............34-11 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxxii Freescale Semiconductor...
Page 33 CPM Interrupt In-Service Register (CISR) ............... 35-9 35.5.5 CPM Interrupt Vector Register (CIVR) ..............35-9 35.6 Interrupt Handler Example—Single-Event Interrupt Source ........35-10 35.7 Interrupt Handler Example—Multiple-Event Interrupt Source........35-10 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxxiii...
Page 34 37.1.4 ATM Transmit Buffer Descriptors (TxBDs).............. 37-6 37.2 Receive and Transmit Connection Tables (RCTs and TCTs) ........37-10 37.2.1 Receive Connection Table (RCT)................37-11 37.2.1.1 Port-to-Port Protocol-Specific RCT ..............37-15 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxxiv Freescale Semiconductor...
Page 35 BRC Performance Calculations ................39-12 39.3.4 Performance Monitoring Tables ................39-12 39.3.5 Activating Performance Monitoring................ 39-14 39.3.5.1 Activating Unidirectional Transmit PM .............. 39-14 39.3.5.2 Activating Unidirectional Receive PM..............39-14 39.3.5.3 Activating Bidirectional PM................39-14 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxxv...
Page 36 PHY Transmit Queues ....................40-14 40.8 MPHY Pointing Table (Master Only)................40-14 40.9 APC Priority Levels..................... 40-15 40.10 Combined APC and PTP Programming Example ............40-20 40.11 APC Scheduling Flow ....................40-21 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxxvi Freescale Semiconductor...
Page 37 UTOPIA Features ......................43-1 43.2 UTOPIA Mode Register (UTMODE) ................43-1 43.3 UTOPIA Operation......................43-5 43.3.1 UTOPIA Split Bus ..................... 43-6 43.3.2 UTOPIA Muxed Bus (Master Operation Only) ............43-6 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxxvii...
Page 38 Initialization of Address Translation Mechanism............ 44-27 44.10.3 Initialization of Global AAL2 Structures ..............44-27 44.10.4 Reconfiguring AAL2 Channels ................44-27 44.10.5 Initialization of Timer CU Mechanism (Optional) ..........44-28 44.11 Performance Estimation....................44-28 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xxxviii Freescale Semiconductor...
Page 39 45.3.2.8 Ethernet Control Register (ECNTRL) ..............45-18 45.3.2.9 Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK) ....... 45-19 45.3.2.10 Ethernet Interrupt Vector Register (IVEC) ............45-20 45.3.2.11 RxBD Active Register (R_DES_ACTIVE)............45-21 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xxxix...
Page 40 Execution Units (EUs) ....................46-5 46.9.1 Data Encryption Standard Execution Unit (DEU)............. 46-5 46.9.2 Advanced Encryption Standard Execution Unit (AESU).......... 46-6 46.9.3 Message Digest Execution Unit (MDEU) ..............46-6 46.10 Performance Estimates ....................46-6 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 41 AESU Register Map ....................48-24 48.3.2 AESU Mode Register ....................48-24 48.3.3 AESU Key Size Register ..................48-26 48.3.4 AESU Data Size Register ..................48-27 48.3.5 AESU Reset Control Register.................. 48-28 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 42 50.2 Interrupts ........................50-13 50.2.1 Channel Done Interrupt ................... 50-13 50.2.2 Channel Error Interrupt.................... 50-14 50.2.3 Channel Reset ......................50-14 50.2.3.1 Hardware Reset....................50-14 50.2.3.2 Channel Specific Software Reset................. 50-14 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xlii Freescale Semiconductor...
Page 43 Chapter 53 System Development and Debugging 53.1 Tracking Program Flow ....................53-1 53.1.1 Program Trace Functional Description..............53-2 53.1.2 Instruction Fetch Show Cycle Control............... 53-2 53.1.3 Program Trace Signals....................53-3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xliii...
Page 44 Exiting Debug Mode.................... 53-23 53.3.2 Development Port Communication ................. 53-24 53.3.2.1 Development Port Pins ..................53-24 53.3.2.1.1 Development Serial Clock (DSCK) ..............53-24 53.3.2.1.2 Development Serial Data In (DSDI) ............... 53-24 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xliv Freescale Semiconductor...
Page 45 Development Port Data Register (DPDR) ............53-46 Chapter 54 IEEE 1149.1 Test Access Port 54.1 Overview........................54-1 54.2 TAP Controller....................... 54-2 54.3 Boundary Scan Register....................54-3 54.4 Instruction Register......................54-5 54.4.1 EXTEST........................54-6 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 46 Instructions Sorted by Mnemonic................... D-1 Instructions Sorted by Opcode..................D-9 Instructions Grouped by Functional Categories ............D-17 Instructions Sorted by Form ..................D-27 Instruction Set Legend ....................D-39 Appendix E MPC880 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xlvi Freescale Semiconductor...
Page 47 Parallel Port Registers....................H-5 Appendix I Revision History Revision Changes from Revision 1 to Revision 2 ............I-1 Revision Changes from Revision 0.1 to Revision 1 ............I-1 Glossary of Terms and Abbreviations 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xlvii...
Page 48 Contents Paragraph Page Number Title Number Index 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 xlviii Freescale Semiconductor...
Page 49 IMMU Control Register (MI_CTR) ..................8-14 DMMU Control Register (MD_CTR) .................. 8-15 IMMU/DMMU Effective Page Number Register (Mx_EPN)..........8-16 IMMU Tablewalk Control Register (MI_TWC)..............8-17 8-10 DMMU Tablewalk Control Register (MD_TWC)..............8-18 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xlix...
Page 50 SIU Interrupt Vector Register (SIVEC) ................10-18 10-14 Interrupt Table Handling Example..................10-19 10-15 Software Watchdog Timer Service State Diagram.............. 10-20 10-16 Software Watchdog Timer Block Diagram ................. 10-21 10-17 Software Service Register (SWSR) ..................10-21 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 51 Basic Flow of a Burst Write Cycle..................13-21 13-17 Burst-Write Cycle: 32-Bit Port Size, Zero Wait States ............13-22 13-18 Burst-Inhibit Cycle: 32-Bit Port Size.................. 13-23 13-19 Internal Operand Representation ..................13-24 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 52 Machine A Mode Register/Machine B Mode Register (MxMR) ........15-14 15-11 Memory Command Register (MCR) .................. 15-16 15-12 Memory Data Register (MDR) ................... 15-17 15-13 Memory Address Register (MAR)..................15-17 15-14 Memory Periodic Timer Prescaler Register (MPTPR) ............15-18 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 53 Synchronous External Master: Burst Read Access to Page Mode DRAM......15-60 15-51 Asynchronous External Master Interconnect Example............15-61 15-52 Asynchronous External Master Timing Example ............... 15-62 15-53 Page-Mode DRAM Interface Connection................15-63 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor liii...
Page 54 MPC885 Application Design Example................. 17-4 17-3 CPM Timer Block Diagram ....................17-5 17-4 Timer Cascaded Mode Block Diagram................. 17-7 17-5 Timer Global Configuration Register (TGCR) ..............17-8 17-6 Timer Mode Registers (TMR1–TMR4)................17-9 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 55 20-9 SI RAM Partitioning Using Two TDMs with Dynamic Frames......... 20-12 20-10 SIRAM Entry ........................20-13 20-11 Example Using SI RAMn[SWTR] ..................20-14 20-12 SI Global Mode Register (SIGMR) ..................20-16 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 56 Transmit Out-of-Sequence Register (TOSEQ) ..............22-10 22-5 Data Synchronization Register (DSR) ................22-11 22-6 Protocol-Specific Mode Register for UART (PSMR) ............22-13 22-7 SCC UART Receiving using RxBDs.................. 22-16 22-8 SCC UART RxBD ......................22-17 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 57 Protocol-Specific Mode Register for BISYNC (PSMR) ............ 26-10 26-6 SCC BISYNC RxBD ......................26-11 26-7 SCC BISYNC TxBD ......................26-13 26-8 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ......... 26-15 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lvii...
Page 58 SPI Block Diagram ....................... 30-1 30-2 Single-Master/Multi-Slave Configuration ................30-3 30-3 Multimaster Configuration....................30-5 30-4 SPI Mode Register (SPMODE) .................... 30-6 30-5 SPI Transfer Format with SPMODE[CP] = 0............... 30-7 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lviii Freescale Semiconductor...
Page 59 C Event/Mask Registers (I2CER/I2CMR)................. 32-8 32-10 C Command Register (I2COM) ..................32-8 32-11 C Function Code Registers (RFCR/TFCR)..............32-10 32-12 C Memory Structure......................32-11 32-13 C Receive Buffer Descriptor (RxBD) ................32-12 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 60 Port C Interrupt Control Register (PCINT)................. 34-17 34-16 Port D Data Register (PDDAT)................... 34-19 34-17 Port D Data Direction Register (PDDIR) ................34-19 34-18 Port D Pin Assignment Register (PDPAR) ................ 34-20 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 61 39-3 Management Cell Filtering ....................39-6 39-4 Performance Monitoring Cell Structure (FMCs and BRCs)..........39-8 39-5 FMC Template ........................39-10 39-6 Function-specific Fields of FMCs, Terminated Cells and Optional BRCs......39-10 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 62 Example of the Receive Data Flow of an AAL2 Channel ..........44-19 44-10 AAL2 Parameter RAM ....................... 44-21 44-11 Example Using the External CT Pointer Table to Allocate AAL2 CTs......44-24 44-12 AAL2-Specific Exception Entry Format ................44-25 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxii Freescale Semiconductor...
Page 63 DEU Interrupt Control Register ..................48-10 48-8 DEU EU_GO Register ......................48-12 48-9 MDEU Mode Register ......................48-13 48-10 MDEU Key Size Register ....................48-15 48-11 MDEU Data Size Register ....................48-16 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxiii...
Page 64 Master Error Address Register....................51-7 52-1 CPTR Register........................52-1 52-2 Data Alignment Example...................... 52-4 53-1 Watchpoints and Breakpoint Support in the Core..............53-8 53-2 Instruction Support General Structure ................53-11 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxiv Freescale Semiconductor...
Page 65 PPC-LE Mode Mechanisms....................A-6 MPC880 Block Diagram......................E-2 MPC875 Block Diagram......................F-2 MPC870 Block Diagram......................G-2 ATM Cell Payload Scrambling Mechanism................H-1 Serial ATM Receive Procedure....................H-2 Cell Delineation State Diagram ..................... H-3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 66 Figures Figure Page Number Title Number MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxvi Freescale Semiconductor...
Page 67 Move to/from Condition Register Instructions ..............5-16 5-16 Memory Synchronization Instructions—UISA ..............5-16 5-17 Move from Time Base Instruction ..................5-18 5-18 Memory Synchronization Instructions—VEA..............5-19 5-19 User-Level Cache Instructions....................5-20 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxvii...
Page 68 Number of Replaced EA Bits per Page Size................. 8-11 Level-One Segment Descriptor Format ................8-11 Level-Two (Page) Descriptor Format ................... 8-12 Page Size Selection ....................... 8-13 MPC885-Specific MMU SPRs ..................... 8-13 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxviii Freescale Semiconductor...
Page 69 TBL Field Descriptions....................... 10-24 10-18 TBREFA/TBREFB Field Descriptions ................10-24 10-19 TBSCR Field Descriptions....................10-25 10-20 PISCR Field Descriptions ....................10-26 10-21 PITC Field Descriptions...................... 10-27 10-22 PITR Field Descriptions...................... 10-28 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxix...
Page 70 15-13 UPM Start Address Locations..................... 15-38 15-14 RAM Word Bit Settings ...................... 15-38 15-15 Enabling Byte-Selects ......................15-43 15-16 GPL_x5 Signal Behavior ....................15-44 15-17 MxMR Loop Field Usage ....................15-45 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 71 SDSR Field Descriptions ...................... 19-5 19-4 IDMA Parameter RAM Memory Map.................. 19-7 19-5 DCMR Field Descriptions ....................19-8 19-6 IDSR1/IDSR2 Field Descriptions ..................19-9 19-7 IDMA BD Status and Control Bits ..................19-11 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxi...
Page 72 UART SCCS Field Descriptions..................22-22 22-14 UART Control Characters for S-Records Example ............22-24 23-1 HDLC-Specific SCC Parameter RAM Memory Map ............23-3 23-2 Transmit Commands ......................23-5 23-3 Receive Commands ......................23-5 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxii Freescale Semiconductor...
Page 73 MPC885 Family ........................27-1 27-2 SCC Ethernet Parameter RAM Memory Map ..............27-8 27-3 Transmit Commands ......................27-10 27-4 Receive Commands......................27-11 27-5 Transmission Errors ......................27-14 27-6 Reception Errors ......................... 27-14 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxiii...
Page 74 SMC C/I Channel TxBD Field Descriptions ..............29-35 29-23 SMCE/SMCM Field Descriptions ..................29-36 30-1 SPMODE Field Descriptions ....................30-6 30-2 Example Conventions ......................30-8 30-3 SPIE/SPIM Field Descriptions....................30-9 30-4 SPCOM Field Descriptions....................30-9 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxiv Freescale Semiconductor...
Page 75 PIP Receiver Parameter RAM Memory Map ............... 33-5 33-5 Control Character Table, RCCM, and RCCR Descriptions..........33-7 33-6 PIPC Field Descriptions......................33-8 33-7 PIPE Field Descriptions ...................... 33-10 33-8 PTPR Field Descriptions ..................... 33-11 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxv...
Page 76 CICR Field Descriptions ....................... 35-7 35-4 CIVR Field Descriptions..................... 35-10 37-1 ATM RxBD Field Descriptions..................... 37-4 37-2 ATM TxBD Field Descriptions..................... 37-8 37-3 RCT Field Descriptions ...................... 37-12 37-4 PTP RCT Field Descriptions....................37-16 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxvi Freescale Semiconductor...
Page 77 Port D Pin Assignment......................42-5 42-6 PCMCIA Port A Pin Assignments..................42-6 42-7 PSMR Serial ATM Field Descriptions.................. 42-8 43-1 UTMODE Field Descriptions ....................43-2 43-2 UTOPIA Signal Groups ......................43-5 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxvii...
Page 78 45-29 R_HASH Field Descriptions....................45-31 45-30 X_CNTRL Field Descriptions .................... 45-32 45-31 Hardware Initialization ....................... 45-33 45-32 ECNTRL[ETHER_EN] Deassertion Initialization ............. 45-33 45-33 User Initialization (Before Setting ECNTRL[ETHER_EN]) ..........45-33 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxviii Freescale Semiconductor...
Page 79 Crypto-Channel Pointer Status Register Error Field Definitions.......... 50-9 50-7 Crypto-Channel Pointer Status Register PAIR_PTR Field Values........50-9 50-8 Crypto-Channel Current Descriptor Pointer Register Fields ..........50-10 50-9 Fetch Register Fields......................50-11 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxix...
Page 80 Little-Endian Program/Data Path Between the Register and 16-Bit Memory....... A-4 Little-Endian Program/Data Path between the Register and 8-Bit Memory ......A-5 PPC-LE 3-bit Munging ......................A-6 User-Level Registers.......................C-1 User-Level SPRs ........................C-1 Supervisor-Level Registers .....................C-2 Supervisor-Level SPRs ......................C-2 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxx Freescale Semiconductor...
Page 81 I-Form ..........................D-27 D-31 B-Form ..........................D-27 D-32 SC-Form..........................D-27 D-33 DS-Form..........................D-29 D-34 X-Form..........................D-29 D-35 XL-Form ..........................D-33 D-36 XFX-Form..........................D-33 D-37 XFL-Form ..........................D-34 D-38 XS-Form..........................D-34 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxi...
Page 82 Serial Interface Register Programming Example for Serial ATM ......... H-4 ATM Cell Transmission and Reception Programming Example ........... H-4 TDMA Port Pin Requirements....................H-5 Port Register Programming Example ..................H-5 MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxxii Freescale Semiconductor...
Page 83: About This Book
8 Kbytes 8 Kbytes Up to 2 Serial ATM Appendix E and UTOPIA interface MPC875 8 Kbytes 8 Kbytes — Appendix F MPC870 8 Kbytes 8 Kbytes — Appendix G MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxiii...
Page 84 RISC architecture characteristics, such as pipelining and parallel execution. It includes a table of instruction latencies and lists dependencies and potential bottlenecks. MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxxiv Freescale Semiconductor...
Page 85 MPC885 implementation of the universal asynchronous receiver transmitter (UART) protocol, used for sending low-speed data between devices. — Chapter 23, “SCC HDLC Mode,” describes the MPC885 implementation of the HDLC protocol. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxv...
Page 86 SAR (ESAR) mode, including multiple APC priority levels, port-to-port switching, simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability, relocatable UTOPIA-level-2-compliant interface with added FIFO buffering to reduce the total cell transmission time. MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxxvi Freescale Semiconductor...
Page 87 SEC Lite to oversee the operations of the execution units (EUs), the interface to the host processor, and the management of the crypto-channel. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxvii...
Page 88 Related Documentation The documentation is organized in the following types of documents: • Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture (MPEFPC32B/AD)—Describes resources defined by the PowerPC architecture. MPC885 PowerQUICC Family Reference Manual, Rev. 2 lxxxviii Freescale Semiconductor...
Page 89 MSR[LE] refers to the little-endian mode enable bit in the machine state register. In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor lxxxix...
Page 90 Data address register Decrementer register Direct memory access DPLL Digital phase-locked loop DRAM Dynamic random access memory DSISR Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 91 Least recently used Least-significant byte Least-significant bit Load/store unit Multiply accumulate MESI Modified/exclusive/shared/invalid—cache coherency protocol Memory management unit Most-significant byte Most-significant bit Machine state register Not a number Next instruction address MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 92 Registers available for general purposes SRAM Static random access memory SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 Test access port Time base register Time-division multiplexed Translation lookaside buffer MPC885 PowerQUICC Family Reference Manual, Rev. 2 xcii Freescale Semiconductor...
Page 93 Table iv. Instruction Field Conventions The Architecture Specification Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor xciii...
Page 94 Table iv. Instruction Field Conventions (continued) The Architecture Specification Equivalent to: RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) MPC885 PowerQUICC Family Reference Manual, Rev. 2 xciv Freescale Semiconductor...
Page 95 MSR[LE] refers to the little-endian mode enable bit in the machine state register. In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. Indicates an undefined numerical value MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 96 Machine state register NMSI Nonmultiplexed serial interface Operating environment architecture Open systems interconnection Peripheral component interconnect PCMCIA Personal Computer Memory Card International Association RISC Reduced instruction set computing RTOS Real-time operating system MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 97 Special-purpose register SRAM Static random access memory Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine Virtual environment architecture MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 98 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 99 MPC875 8 Kbyte 8 Kbyte Up to 1 – MPC870 8 Kbyte 8 Kbyte — — – The SCC may be used if any one of the FECs is not used. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 100 — Supports full-duplex UTOPIA operation, both master (ATM side) and slave (PHY side), using a 'split' bus — AAL2/VBR functionality is ROM-resident • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) • 32 address lines MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 101 – ECB and CBC modes for both DES and 3DES — AESU—Advanced encryption standard unit – Implements the Rijndael symmetric-key cipher – ECB, CBC, and counter modes – 128-, 192-, or 256-bit key lengths MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 102 — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 103 — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, and user-defined — one- or eight-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 104 MPC875/MPC870 comes in a 256-pin ball grid array The MPC885 family is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 105 Media Access Control Parallel Interface Port Timers Channels and UTOPIA SCC1 SCC1 SCC2 SCC2 SCC3 SCC4 SMC1 SMC1 SMC2 SMC2 Time Slot Assigner Serial Interface Serial Interface Figure 1-1. MPC866P Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 106 Virtual IDMA Control and Program Parallel Interface Port Timers Serial DMAs MIII / RMII SCC4/ SCC2 SCC3 SMC1 SMC2 UTOPIA Time-Slot Assigner Serial Interface Serial Interface Figure 1-2. MPC885 Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 107 Media Access Control Parallel Interface Port Timers Channels and UTOPIA SCC1 SCC1 SCC2 SCC2 SCC3 SCC4 SMC1 SMC1 SMC2 SMC2 Time Slot Assigner Serial Interface Serial Interface Figure 1-3. MPC866P Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 108 Virtual IDMA Control and Program Parallel Interface Port Timers Serial DMAs MIII / RMII SCC4/ SCC3 SMC1 SMC2 UTOPIA Time-Slot Assigner Serial Interface Serial Interface Figure 1-4. MPC880 Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 1-10 Freescale Semiconductor...
Page 109 4 Baud Rate Media Access 32-Bit RISC Controller Generators Virtual IDMA Control and Program Parallel Interface Port Timers Serial DMAs MIII / RMII SCC4 SMC1 Time-Slot Assigner Serial Interface Serial Interface MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 1-11...
Page 110 Control Parallel Interface Port Timers Channels and UTOPIA SCC1 SCC1 SCC2 SCC2 SCC3 SCC4 SMC1 SMC1 SMC2 SMC2 Time Slot Assigner Serial Interface Serial Interface Figure 1-5. MPC866P Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 1-12 Freescale Semiconductor...
Page 111 SMC1 SMC1 SMC2 SMC2 Time Slot Assigner Serial Interface Serial Interface Figure 1-6. MPC866P Block Diagram Figure 1-7. MPC875 Block Diagram The MPC870 block diagram is shown in Figure 1-9. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 1-13...
Page 112 Control Parallel Interface Port Timers Channels and UTOPIA SCC1 SCC1 SCC2 SCC2 SCC3 SCC4 SMC1 SMC1 SMC2 SMC2 Time Slot Assigner Serial Interface Serial Interface Figure 1-8. MPC866P Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 1-14 Freescale Semiconductor...
Page 113 The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. The core interface to the internal and external buses is 32 bits wide. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 1-15...
Page 114 The MPC885 supports a glueless interface to one bank of DRAM, while external buffers are required for additional memory banks. The refresh unit provides CAS before RAS, a programmable refresh timer, refresh active during external reset, disable MPC885 PowerQUICC Family Reference Manual, Rev. 2 1-16 Freescale Semiconductor...
Page 115: Power Management
8xx/IF module. Crypto- Channel FIFO FIFO Bus/IF Unit Controller MDEU AESU FIFO Figure 1-10. Security Engine Functional Blocks MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 1-17...
Page 116 The MPC885 family is the next generation MPC8xx family of devices. Like its predecessor it implements a dual-processor architecture, which provides both a high-performance, general-purpose processor for application programming use as well as a special-purpose communication processor (CPM) uniquely designed for communications applications. MPC885 PowerQUICC Family Reference Manual, Rev. 2 1-18 Freescale Semiconductor...
Page 117 The MPC885 family can be used as an adaptable ATM controller suited for a variety of applications, including the following: • DSLAM line cards • Access concentrators • LAN/WAN switches • Hubs/Gateways • PBX systems • Wireless base stations MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 1-19...
Page 118 MPC885 Overview MPC885 PowerQUICC Family Reference Manual, Rev. 2 1-20 Freescale Semiconductor...
Page 119 PBR2—PCMCIA interface base register 2 32 bits 16.4.5/16-14 POR2—PCMCIA interface option register 2 32 bits 16.4.6/16-14 PBR3—PCMCIA interface base register 3 32 bits 16.4.5/16-14 POR3—PCMCIA interface option register 3 32 bits 16.4.6/16-14 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 120 32 bits 15.4.1/15-8 OR4—Option register bank 4 32 bits 15.4.2/15-11 BR5—Base register bank 5 32 bits 15.4.1/15-8 OR5—Option register bank 5 32 bits 15.4.2/15-11 BR6—Base register bank 6 32 bits 15.4.1/15-8 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 121 PISCR—Periodic interrupt status and control register 16 bits 10.10.1/10-26 242–243 Reserved 2 bytes — PITC—Periodic interrupt count registerA 32 bits 10.10.2/10-27 PITR—Periodic interrupt timer register 32 bits 10.10.3/10-28 24C–27F Reserved 52 bytes — MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 122 8 bits 32.4.1/32-6 861–863 Reserved 3 bytes — I2ADD—I C address register 8 bits 32.4.2/32-7 865–867 Reserved 3 bytes — I2BRG—I C BRG register 8 bits 32.4.3/32-7 869–86B Reserved 3 bytes — MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 123 CISR—CPM in-service register 32 bits 35.5.4/35-9 Input/Output Port PADIR—Port A data direction register 16 bits 34.2.1.3/34-4 PAPAR—Port A pin assignment register 16 bits 34.2.1.4/34-5 PAODR—Port A open drain register 16 bits 34.2.1.1/34-3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 124 TRR3—Timer 3 reference register 16 bits 17.2.4.1/17-10 TRR4—Timer 4 reference register 16 bits 17.2.4.1/17-10 TCR3—Timer 3 capture register 16 bits 17.2.4.2/17-10 TCR4—Timer 4 capture register 16 bits 17.2.4.2/17-10 TCN3—Timer 3 counter 16 bits 17.2.4.3/17-10 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 125 Reserved 20 bytes — Baud Rate Generators BRGC1—BRG1 configuration register 32 bits 20.4.1/20-37 BRGC2—BRG2 configuration register 32 bits 20.4.1/20-37 BRGC3—BRG3 configuration register 32 bits 20.4.1/20-37 BRGC4—BRG4 configuration register 32 bits 20.4.1/20-37 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 126 16 bits 21.2.4/21-10 DSR2—SCC2 data synchronization register 16 bits 21.2.3/21-10 SCCE2—SCC2 event register 16 bits 22.20/22-22 (UART) 23.11/23-12 (HDLC) 25.13.1/25-8 (Asynchronous HDLC) 26.15/26-15 (BISYNC) 28.12/28-11 (Transparent) A32–A33 Reserved 16 bits — MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 127 (UART) 23.12/23-14 (HDLC) 26.15/26-15 (BISYNC) 28.12/28-11 (Transparent) A58–A5F Reserved 8 bytes — Serial Communications Controller 4 (SCC4) GSMR_L4—SCC4 general mode register 32 bits 21.2.1/21-3 GSMR_H4—SCC4 general mode register 32 bits 21.2.1/21-3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 128 Serial Management Controller 2 (SMC2) SMCMR2—SMC2 mode register 16 bits 29.2.1/29-2 A94–A95 Reserved 2 bytes — SMCE2—SMC2 event register 8 bits 29.3.12/29-18 (UART) 29.4.11/29-29 (Transparent) 29.5.9/29-35 (GCI) A97–A99 Reserved 3 bytes — MPC885 PowerQUICC Family Reference Manual, Rev. 2 2-10 Freescale Semiconductor...
Page 129 32 bits 34.6.1.1/34-22 PEDAT — Port E data register 32 bits 34.5.1.1/34-18 Communications Processor Timing Register - Contains RMII Timing for the FECs CPTR — CPTR Register 32 bits 45.3.1/45-11, 52.1/52-1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 2-11...
Page 130 R_DES_ACTIVE 32 bits 45.3.2.11/45-21 X_DES_ACTIVE 32 bits 45.3.2.12/45-22 E58–E7F Reserved 40 bytes — MII_DATA 32 bits 45.3.2.13/45-22 MII_SPEED 32 bits 45.3.2.14/45-24 E88–ECB Reserved 68 bytes — R_BOUND 32 bits 45.3.2.15/45-25 MPC885 PowerQUICC Family Reference Manual, Rev. 2 2-12 Freescale Semiconductor...
Page 131 1E50 R2_DES_ACTIVE 32 bits 45.3.2.11/45-21 1E54 X2_DES_ACTIVE 32 bits 45.3.2.12/45-22 1E58–1E7F Reserved 40 bytes — 1E80 MII2_DATA 32 bits 45.3.2.13/45-22 1E84 MII2_SPEED 32 bits 45.3.2.14/45-24 1E88–1ECB Reserved 68 bytes — MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 2-13...
Page 132 8 bytes — 01030 Controller Master Control 64 bits 51.1.5/51-6 01038 Controller Master TEA Address 64 bits 51.1.6/51-7 01040–02007 Reserved 4040 bytes — 02008 Channel Config Register 64 bits 50.1.1/50-2 MPC885 PowerQUICC Family Reference Manual, Rev. 2 2-14 Freescale Semiconductor...
Page 133 05020–05027 Reserved 8 bytes — 05028 Status register 64 bits 48.1.6/48-6 05030 Interrupt status register 64 bits 48.1.7/48-7 05038 Interrupt control register 64 bits 48.1.8/48-9 05040–0504F Reserved 16 bytes — MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 2-15...
Page 134 2048 bytes 48.2.12/48-23 07000–07FFF Reserved 4096 bytes — The registers are 64 bits long, but the upper 32 bits of each register must be cleared when the register is initialized. MPC885 PowerQUICC Family Reference Manual, Rev. 2 2-16 Freescale Semiconductor...
Page 135 MPC885 instruction unit, and provides ways to take greatest advantage of its RISC architecture characteristics, such as pipelining and parallel execution. It includes a table of instruction latencies and lists dependencies and potential bottlenecks. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor II-1...
Page 136 Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale processors. Additional literature is published as new processors become available. For a current list of documentation, refer to http://www.freescale.com. MPC885 PowerQUICC Family Reference Manual, Rev. 2 II-2 Freescale Semiconductor...
Page 137 Table II-1. Acronyms and Abbreviated Terms Term Meaning Arithmetic logic unit BIST Built-in self test Branch processing unit BUID Bus unit ID Condition register Cyclic redundancy check Count register DABR Data address breakpoint register MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor II-3...
Page 138 No operation Operating environment architecture Peripheral component interconnect Processor version register RISC Reduced instruction set computing RTOS Real-time operating system RWITM Read with intent to modify Receive SIMM Signed immediate value MPC885 PowerQUICC Family Reference Manual, Rev. 2 II-4 Freescale Semiconductor...
Page 139 Interrupt Exception Privileged mode (or privileged state) Supervisor-level privilege Problem mode (or problem state) User-level privilege Real address Physical address Relocation Translation Storage (locations) Memory Storage (the act of) Access MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor II-5...
Page 140 Equivalent To: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) MPC885 PowerQUICC Family Reference Manual, Rev. 2 II-6 Freescale Semiconductor...
Page 141 64-bit addressing, multiprocessing, floating-point arithmetic, and some memory management features. The core also implements MPC885-specific development support features such as breakpoint and watchpoint mechanisms, program-flow tracking data generation, and debug mode operation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 142 Support for 64-bit addressing. The architecture supports both 32- or 64-bit implementations. This document describes the 32-bit portion of the PowerPC architecture. For information about the 64-bit architecture, see Programming Environments Manual for Implementations of the PowerPC Architecture. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 143 Programming Environments Manual for Implementations of the PowerPC Architecture. For details of the MPC8xx core as an implementation of the PowerPC architecture, see Section 3.7, “The MPC885 and Implementation of the PowerPC Architecture.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 144 ITLB • Time Base Counter • Decrementer • JTAG 32-Bit • BDM Interface Kbyte Kbyte Tags Tags • Clock Multiplier D-Cache I-Cache U-Bus Interface Figure 3-1. Block Diagram of the Core MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 145 — Load/store unit (LSU)—Implements all load and store instructions except floating-point load/store instructions. Note that because the MPC885 does not implement floating-point load and store instructions, this document refers to integer load/store instructions simply as load/store instructions. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 146 This information is used to enable out-of-order completion of instructions and ensure a precise exception model. An instruction can be retired after all instructions ahead of it have retired and it updates the architected destination registers without taking an exception. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 147 To reduce the latency caused by misprediction, branch instructions allow the programmer to indicate whether a branch is likely to be taken. This is called static branch prediction. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 148 BC with positive offset Fall through Taken BCLR or BCCTR (LR or CTR) address ready Fall through Taken BCLR or BCCTR (LR or CTR) address not ready Wait Wait B (unconditional branch) Taken Taken MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 149 No prediction is done for branches to the link register or count register if the target address is not ready (see Table 3-1 for details). 3.6.2 Integer Unit The core implements the following types of integer instructions: • Arithmetic instructions • Compare instructions MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 150 2-entry, 32-bit queue that holds integer data. The LSU has a dedicated writeback bus so that loaded data received from the internal bus is written directly back to the GPRs. MPC885 PowerQUICC Family Reference Manual, Rev. 2 3-10 Freescale Semiconductor...
Page 151 For load/store with update instructions, the destination address register is written back on the following clock cycle, regardless of the address queue’s state. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 3-11...
Page 152 Table 3-2. Bus Cycles Needed for Single-Register Load/Store Accesses Transfer Size Transfer Address (Last Two Bits) Number of Bus Cycles Transfer Type Address/Size Byte 0x00 Aligned 0x00/byte 0x01 Aligned 0x01/byte 0x02 Aligned 0x02/byte 0x03 Aligned 0x03/byte MPC885 PowerQUICC Family Reference Manual, Rev. 2 3-12 Freescale Semiconductor...
Page 153 If a new lwarx instruction address tenure executes successfully, it replaces any previous reservation address at the appropriate snoop logic. However, executing an stwcx. instruction cancels the reservation unless an alignment exception is detected. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 3-13...
Page 154 Branch prediction The core uses the y bit to predict path for prefetch. Prediction is only done for not-ready branch conditions. No prediction is done for branches to the link or count register if the target address is not ready (see Table 3-1). MPC885 PowerQUICC Family Reference Manual, Rev. 2 3-14 Freescale Semiconductor...
Page 155 Little-endian byte The LSU supports little-endian byte ordering as specified in the UISA. In little-endian mode, trying ordering to execute an unaligned individual scalar or multiple/string access causes an alignment exception. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 3-15...
Page 156 The time base functions as defined by the VEA and supports an additional implementation-specific exception. The time base is described in Chapter 10, “System Interface Unit,” and in Chapter 14, “Clocks and Power Control.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 3-16 Freescale Semiconductor...
Page 157 TLB error exception mechanism when writing to an unmodified page. Memory Two protection modes are supported by the MPC885: protection • Domain manager mode • PowerPC mode Chapter 8, “Memory Management Unit.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 3-17...
Page 158 The MPC8xx Core MPC885 PowerQUICC Family Reference Manual, Rev. 2 3-18 Freescale Semiconductor...
Page 159 (the floating-point register file (FPRs) and the floating-point status and control register (FPSCR)). User-level PowerPC registers are listed in Table 4-1 Table 4-2. Table 4-2 lists user-level special-purpose registers (SPRs). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 160 Specified fields of the CR can be set from a GPR by using the mtcrf instruction. • An mcrf instruction can move the contents of XER[0–3] to a CR field. • An mcrxr instruction can copy a specified XER field to a specified CR field. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 161 Figure 4-2 shows XER bit assignments. Settings are based on the final result produced by executing an instruction. Field SO — Reset 0000_0000_0000_0000 Field — BCNT Reset 0000_0000_0000_0000 Figure 4-2. XER Register MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 162 All supervisor-level registers implemented on the MPC885 are SPRs, except for the machine state register (MSR), described in Table 4-5. Table 4-5. Supervisor-Level PowerPC Registers Description Name Reference/Section Serialize Access Machine state register Section 4.1.2.3.1, “Machine State Register (MSR).” Write fetch sync MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 163 The BAR has a valid value only when a data breakpoint exception is taken. At any other time, its value is boundedly undefined. (This term is defined very MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 164 The 32-bit machine state register (MSR) is used to configure such parameters as the privilege level, whether translation is enabled, and the endian mode. It can be read by the mfmsr instruction and modified by the mtmsr, sc, and rfi instructions. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 165 1 The processor can execute floating-point instructions. (This setting is invalid on the MPC885.) Machine check enable 0 Machine check exceptions are disabled. 1 Machine check exceptions are enabled. — Reserved MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 166 These bits are loaded into SRR1 when an exception is taken. These bits are written back into the MSR when an rfi is executed. 4.1.2.3.2 Processor Version Register The value of the PVR register’s version field is 0x0050. The value of the revision field is incremented each time the core is revised. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 167 11001 10000 MI_CAM Section 8.8.12.1, “IMMU CAM Entry Write (as a store) Read Register (MI_CAM)” 11001 10001 MI_RAM0 Section 8.8.12.2, “IMMU RAM Entry Write (as a store) Read Register 0 (MI_RAM0)” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 168 Fetch sync on write 00100 10001 CMPB Fetch sync on write 00100 10010 CMPC Fetch sync on write 00100 10011 CMPD Fetch sync on write 00100 10100 Fetch sync on write MPC885 PowerQUICC Family Reference Manual, Rev. 2 4-10 Freescale Semiconductor...
Page 169 Table 4-11. Addresses of SPRs Located Outside of the Core Address Lines 0:17 18:22 23:27 28:31 0...0 SPR[0–4] SPR[5–9] 0000 Address errors in this tenure cause a software emulation exception. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 4-11...
Page 170 • COUNTB[16–31]—Cleared • ICR—Cleared (no exception occurred) • DER[2,14,28–31]—Set (all debug-specific exceptions cause debug mode entry) Reset values for memory-mapped registers are provided with individual register descriptions throughout this manual. MPC885 PowerQUICC Family Reference Manual, Rev. 2 4-12 Freescale Semiconductor...
Page 171 Quad word 16 bytes 0000 Note: An “x” in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 172 Integer instructions operate on word operands. The architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half word, and word operand loads and stores between memory and a set of 32 general-purpose registers (GPRs). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 173 Defined instructions are guaranteed to be supported in all MPC8xx implementations, except as stated in the instruction descriptions in Chapter 8, “Instruction Set,” in The Programming Environments Manual. The MPC885 provides hardware support for all instructions defined for 32-bit implementations, except floating-point instructions. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 174 5.2.1.4 Reserved Instruction Class Reserved instructions are allocated to specific implementation-dependent purposes not defined by the architecture. An attempt to execute an unimplemented reserved instruction invokes the illegal instruction MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 175 Branch instructions have three categories of effective address generation: • Immediate • Link register indirect • Count register indirect Refer to Section 5.2.4.3.1, “Branch Instruction Address Calculation,” for further discussion of branch instruction effective address generation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 176 Note that the privilege level of the mfspr and mtspr instructions depends on the SPR encoding. • An attempt to access memory that is not available (page fault) causes the ISI exception handler to be invoked. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 177 Table 5-2 lists the integer arithmetic instructions for the MPC885. Table 5-2. Integer Arithmetic Instructions Name Mnemonic Syntax Add Immediate addi rD,rA,SIMM Add Immediate Shifted addis rD,rA,SIMM add (add.addo addo.) rD,rA,rB MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 178 UIMM operand, the SIMM operand, or the contents of rB. The comparison is signed for the cmpi and cmp instructions, and unsigned for the cmpli and cmpl instructions. Table 5-3 lists the integer compare instructions. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 179 OR Immediate Shifted oris rA,rS,UIMM XOR Immediate xori rA,rS,UIMM XOR Immediate Shifted xoris rA,rS,UIMM and (and.) rA,rS,rB or (or.) rA,rS,rB xor (xor.) rA,rS,rB NAND nand (nand.) rA,rS,rB nor (nor.) rA,rS,rB MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 180 Name Mnemonic Syntax Shift Left Word slw (slw.) rA,rS,rB Shift Right Word srw (srw.) rA,rS,rB Shift Right Algebraic Word Immediate srawi (srawi.) rA,rS,SH Shift Right Algebraic Word sraw (sraw.) rA,rS,rB MPC885 PowerQUICC Family Reference Manual, Rev. 2 5-10 Freescale Semiconductor...
Page 181 Load Half Word Algebraic rD,d(rA) Load Half Word Algebraic Indexed lhax rD,rA,rB Load Half Word Algebraic with Update lhau rD,d(rA) Load Half Word Algebraic with Update Indexed lhaux rD,rA,rB MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 5-11...
Page 182 Likewise, when used in a system operating with little-endian byte order, these instructions have the effect of loading and storing data in big-endian order. For more information about MPC885 PowerQUICC Family Reference Manual, Rev. 2 5-12 Freescale Semiconductor...
Page 183 Table 5-11. Integer Load and Store String Instructions Name Mnemonic Syntax Load String Word Immediate lswi rD,rA,NB Load String Word Indexed lswx rD,rA,rB Store String Word Immediate stswi rS,rA,NB Store String Word Indexed stswx rS,rA,rB MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 5-13...
Page 184 Branch instructions compute the effective address (EA) of the next instruction address using the following addressing modes: • Branch relative • Branch conditional to relative address • Branch to absolute address • Branch conditional to absolute address MPC885 PowerQUICC Family Reference Manual, Rev. 2 5-14 Freescale Semiconductor...
Page 185 If any of the conditions tested by a trap instruction are met, the system trap handler is invoked. If the tested conditions are not met, instruction execution continues normally. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 5-15...
Page 186 Touch load operations (dcbt and dcbtst) are required to complete at least through address translation, but not required to complete on the bus. MPC885 PowerQUICC Family Reference Manual, Rev. 2 5-16 Freescale Semiconductor...
Page 187 It does not affect fetching; instructions continue to be fetched up to the instruction queue limit, but dispatch stalls until the sync finishes. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 5-17...
Page 188 Chapter 7, “Instruction and Data Caches,” for additional information about these instructions and about related aspects of memory synchronization. Table 5-18 lists the VEA memory synchronization instructions for the MPC885. MPC885 PowerQUICC Family Reference Manual, Rev. 2 5-18 Freescale Semiconductor...
Page 189 If the programmer needs to ensure that cache or other instructions have been performed with respect to all other processors and system mechanisms, a sync instruction must be placed in the program following those instructions. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 5-19...
Page 190 Processor control instructions read from and write to the condition register (CR), machine state register (MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL). MPC885 PowerQUICC Family Reference Manual, Rev. 2 5-20 Freescale Semiconductor...
Page 191 5.2.6.3 Memory Control Instructions—OEA This section describes memory control instructions, which include the following types: • Cache management instructions • TLB management instructions MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 5-21...
Page 192 MPC885 Instruction Set MPC885 PowerQUICC Family Reference Manual, Rev. 2 5-22 Freescale Semiconductor...
Page 193 This also implies that a store or nonspeculative load instruction is not issued to the load/store bus until all MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 194 Section 6.1.2.8, “Decrementer Exception (0x00900).” 0x00A00– Reserved — 0x00B00 0x00C00 System call Section 6.1.2.9, “System Call Exception (0x00C00).” 0x00D00 Trace Section 6.1.2.10, “Trace Exception (0x00D00).” 0x00E00 Floating-point assist Section 6.1.2.11, “Floating-Point Assist Exception.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 195 Trace bit asserted ITLB miss Instruction MMU TLB miss ITLB error Instruction MMU protection/translation error Machine check Fetch error Debug instruction breakpoint Match detection Software emulation exception Attempt to invoke unimplemented feature MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 196 A system reset interrupt occurs when IRQ0 is asserted. When the exception is taken, processing begins at offset 0x00100. A hard or soft reset also causes program execution to begin fetching at 0x00100 after the associated reset actions. Table 6-4 shows register settings. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 197 Set to bits 21-24 of the instruction if X-form instruction and to bits 1-4 if D-form. 22–31 Set to bits 6-15 of the instruction. When the load/store bus is used, DAR holds the EA of the data access that caused the exception. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 198 If it is important to minimize exception latency, exception handlers should save the machine context and reenable exceptions as quickly as possible so pending external exceptions are handled quickly. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 199 Loaded with equivalent bits from the MSR 10–15 Cleared 16–31 Loaded with equivalent bits from the MSR Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 200 (MSR[PR] is set). It is also generated for mtspr or mfspr instructions that have an invalid SPR MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 201 • Loading a GPR from the decrementer does not affect the decrementer. • Storing a GPR value to DEC replaces the DEC contents with the value in the GPR. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 202 MSR[IP]. As with most other exceptions, this exception is context-synchronizing. Refer to Section 5.2.2.3.1, “Context Synchronization,” regarding actions performed by a context-synchronizing operation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 6-10 Freescale Semiconductor...
Page 203 Execution resumes at offset 0x00D00 from the base address indicated by MSR[IP]. 6.1.2.11 Floating-Point Assist Exception The floating-point assist exception is not generated by the MPC885. Attempting to execute a floating-point causes an instruction implementation-specific software emulation exception. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 6-11...
Page 204 This type of exception occurs if MSR[IR] = 1 and an attempt is made to fetch an instruction from a page whose effective page number cannot be translated by TLB. As shown in Table 6-13, the following registers are set: MPC885 PowerQUICC Family Reference Manual, Rev. 2 6-12 Freescale Semiconductor...
Page 205 OEA, the concept of segment is retained as the memory space accessible to the level-one table descriptors. • The fetch access violates memory protection. • The fetch access is to guarded memory. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 6-13...
Page 206 10–15 0 Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI]. No change No change Copied from the ILE setting of the interrupted process Other MPC885 PowerQUICC Family Reference Manual, Rev. 2 6-14 Freescale Semiconductor...
Page 207 For L-bus breakpoint conditions. Set to the EA of the data access as computed by the instruction that caused the exception. DSISR For L-bus breakpoint conditions. Do not change. For L-bus breakpoint conditions. Do not change. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 6-15...
Page 208 Interrupts should also be MPC885 PowerQUICC Family Reference Manual, Rev. 2 6-16 Freescale Semiconductor...
Page 209 External interrupt disable, but other exception are recoverable: End of handler’s prologue, keep external nested interrupts disabled; Start of critical code segment in which external interrupts are disabled Nonrecoverable interrupt: Start of handler’s epilogue MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 6-17...
Page 210 ••• Stage Fetch (in IQ) In dispatch entry (IQ0) Execute Complete (In CQ) In retirement entry (CQ0) Instruction Queue Completion Queue Figure 6-1. Exception Latency MPC885 PowerQUICC Family Reference Manual, Rev. 2 6-18 Freescale Semiconductor...
Page 211 Faulting instruction TLB miss/error Before Faulting fetch or load/store Other noninstruction-related exceptions Before Next instruction to execute Alignment Load/store Before Faulting instruction Privileged instruction Any privileged Before Faulting instruction instruction MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 6-19...
Page 212 Faulting instruction Debug L- breakpoint Load/store After Faulting instruction + 4 Software emulation Before Faulting instruction Floating-point unavailable Floating-point Before Faulting instruction Implementation-specific exceptions not defined by the PowerPC architecture. MPC885 PowerQUICC Family Reference Manual, Rev. 2 6-20 Freescale Semiconductor...
Page 213 — Modified-valid (sometimes called ‘modified’) — Unmodified-valid (sometimes called ‘exclusive’) — Invalid • A single state bit for each instruction cache block allows encoding for two possible states: — Valid — Invalid MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 214 The MPC885 instruction cache is organized as 256 sets of two blocks, as shown in Figure 7-1. Each block consists of 16 bytes, a single state bit, a lock bit, and an address tag. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 215 The instruction cache implements a single state bit for each cache block that indicates whether the cache block is valid or invalid. The MPC885 does not support snooping of the instruction cache. All memory is MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 216 The MPC885 data cache is organized as 256 sets of two blocks as shown in Figure 7-2. Each block consists of four words, two state bits, a lock bit, and an address tag. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 217 Note that address bits A[20–27] provide the index to select a cache set for the MPC885. Bits A[28–29] select a word within a block. The tags consist of the high-order physical address bits PA[0–19]. Address translation occurs in parallel with set selection (from A[20–27]). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 218 7-3, has an SPR encoding of 560. Field IEN — — CCER1 CCER2 — Reset — — — — — — — Field — Reset — — Figure 7-3. Instruction Cache Control and Status Register (IC_CST) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 219 Reading this bit clears it. 12–31 — Reserved The IC_ADR register, shown in Figure 7-4, has an SPR encoding of 561. Field Reset — Figure 7-4. Instruction Cache Address Register (IC_ADR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 220 1. Write the address of the data or tag to be read to the IC_ADR according to the format in Table 7-5. Note that it is also possible to read this register for debugging purposes. 2. Read the IC_DAT register. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 221 To load and lock one or more cache blocks: 1. Read the IC_CST error type bits to clear them. 2. Write the address of the cache block to be locked to the IC_ADR register. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 222 If a block is not locked or if it is marked invalid, no operation is performed. There are no error cases for the unlock all command The instruction cache performs the unlock all command in one clock cycle. MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-10 Freescale Semiconductor...
Page 223 Field DEN DFWT LES — — CCER1 CCER2 — Reset — — — — — — — Field — Reset — — Figure 7-6. Data Cache Control and Status Register (DC_CST) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-11...
Page 224 0 No error detected 1 Error detected Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected. Reading this bit clears it. MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-12 Freescale Semiconductor...
Page 225 Section 7.3.2.1, “Reading Data Cache Tags and Copyback Buffer,” for more information. The DC_DAT register, shown in Figure 7-8, has an SPR encoding of 570. Field Reset — Figure 7-8. Data Cache Data Port Register (DC_DAT) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-13...
Page 226 The last copyback address or data buffer can be read by using the copyback buffer read command (DC_ADR[18] = 1). The copyback buffer select field (DC_ADR[20–27]), shown in Table 7-12, determines which word of the cache block in the copyback buffer is read. MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-14 Freescale Semiconductor...
Page 227 1. Read the DC_CST error type bits to clear them. 2. Write the address of the cache block to be locked to the DC_ADR register. 3. Write the load-and-lock cache block command (DC_CST[CMD] = 0b0110) to the DC_CST register. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-15...
Page 228 As a result of the invalidate all command, the LRU bits of all cache blocks point to either the unlocked way or to way 0 if both ways are unlocked. There are no error cases for the invalidate all command. MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-16 Freescale Semiconductor...
Page 229 This command is not privileged and has no associated error cases. The instruction cache performs the icbi instruction in one clock cycle. To accurately calculate the latency of this instruction, bus latency should be taken into consideration. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-17...
Page 230 The function of this instruction is independent of the memory/cache access attributes. The dcbst instruction executes regardless of whether the cache is disabled or the cache block is locked. MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-18 Freescale Semiconductor...
Page 231 0–19 of the instruction address. If a match is found and the matched entry is valid, it is a cache hit. If no tag matches or the matched tag is not valid, it is a cache miss. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-19...
Page 232 • The instruction cache supports hits under misses (allows servicing hits while a previous miss is being fetched from the external bus) MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-20 Freescale Semiconductor...
Page 233 These instructions may be discarded later if it turns out that the machine has followed the wrong path. To minimize power consumption, the MPC885 instruction cache does not initiate a miss sequence in most MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-21...
Page 234 When the data MMU is disabled (MSR[DR] = 0), the data cache operates as defined by the default data memory access attributes. The default state of the write-through/write-back attribute is determined by MD_CTR[WTDEF]; the caching-inhibited/caching-allowed attribute is determined by MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-22 Freescale Semiconductor...
Page 235 The selection algorithm gives first priority to invalid blocks. If both blocks in the set are marked invalid, the block in way 0 is selected. If neither of the two blocks in the selected set are invalid, the least recently MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-23...
Page 236 The state and LRU bits remain unchanged. If a bus error is encountered during the write operation to memory, a machine check exception is generated. MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-24 Freescale Semiconductor...
Page 237 (the copyback error is an imprecise exception). The address and data in the copyback buffer can be read as specified in Section 7.3.2.1, “Reading Data Cache Tags and Copyback Buffer.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-25...
Page 238 See Section 13.4.9, “Memory Reservation,” for more information. Internal to the MPC885, the data cache has snoop logic to MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-26 Freescale Semiconductor...
Page 239 The development port is a relatively inexpensive interface that allows a development system to operate in a lower frequency than the core’s frequency and controls system activity when the core is in debug mode. See Section 53.3, “Development System Interface,” for more information. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-27...
Page 240 When the internal freeze signal is asserted, store hits and misses are treated as write-through accesses, but the LRU bits in the data cache array are not updated. For the dcbz instruction, data is written both into data MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-28 Freescale Semiconductor...
Page 241 LRU bits in the data cache array are not updated. For the dcbst/dcbf/dcbi instructions, the data cache and memory are updated according to the PowerPC architecture, but the LRU bits in the data cache array are not updated. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 7-29...
Page 242 Instruction and Data Caches MPC885 PowerQUICC Family Reference Manual, Rev. 2 7-30 Freescale Semiconductor...
Page 243 — Implementation-specific exceptions—ITLB and DTLB miss exceptions, ITLB and DTLB error exceptions — Supports PowerPC tlbie and tlbia instructions. The tlbsync instruction, which is optional to PowerPC architecture implementations, is not supported and is treated as a no-op. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 244 The default for whether accesses are cache-inhibited are programmed through Mx_CTR[CIDEF]. Data accesses can be either write-through (memory writes go both to the cache and to external memory) or write-back (memory writes directly affect the cache only and MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 245 EPN is written and the old one is invalidated. The MMU supports a multiple virtual address space model. Each translation is associated with an ASID, which must equal the address space ID (CASID) for a translation to be valid. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 246 DMMU does not implement a fast TLB mechanism. The DTLB is accessed for each transfer simultaneously with the data cache tag read, hence there is no time penalty. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 247 TLB, the EA and CASID are compared with each entry’s EPN and ASID. The CASID is compared only when the matching entry is programmed as unshared. See Table 8-12 Table 8-13. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 248 Kp and Ks bits for the corresponding segment defined by the level-one table descriptor. In domain manager mode, each field holds override information over the page protection setting: no override, no access override, and free access override. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 249 — To define a 4-Kbyte page with uniform protection, create four level-two descriptors for the 4-Kbyte page, each with subpage validity flags set to 0b1111. All other fields of the level-two descriptors must also be the same for each of these entries. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 250 Translation Table Structure The MMU hardware supports a two-level software tablewalk. Other table structures are not precluded. Figure 8-4 shows the two-level translation table when MD_CTR[TWAM] = 1 (4-Kbyte resolution of protection). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 251 Identical Entries Required in Level-Two Table Page Size MD_CTR[TWAM] = 0 MD_CTR[TWAM] = 1 MD_CTR[TWAM] = 0 MD_CTR[TWAM] = 1 1 Kbyte — — 4 Kbytes 16 Kbytes 512 Kbytes 8 Mbytes MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 252 EA[0–11] to get the level-one page descriptor. As shown in Table 8-1, 8-Mbyte pages must have eight identical entries in the level-one table for EA[9–11]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-10 Freescale Semiconductor...
Page 253 11 8 Mbyte Writethrough attribute for entry 0 Copyback cache policy region (default) 1 Writethrough cache policy region Level-one segment valid bit 0 Segment is not valid 1 Segment is valid MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-11...
Page 254 0 Caching is allowed. 1 Caching is inhibited. Page valid bit For pages larger than 4 Kbytes in mode 2, PP in bits [22–23,24–25,26–27] must equal the PP in bits [20–21]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-12 Freescale Semiconductor...
Page 255 DMMU effective number register MI_TWC IMMU tablewalk control register 8.8.4 MD_TWC DMMU tablewalk control register 8.8.5 MI_RPN IMMU real (physical) page number port 8.8.6 MD_RPN DMMU real (physical) page number register 8.8.7 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-13...
Page 256 The IMMU control register (MI_CTR), shown in Figure 8-6, controls IMMU operation. Field GPM PPM CIDEF — RSV4I — PPCS — Reset Field — ITLB_INDX — Reset Figure 8-6. IMMU Control Register (MI_CTR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-14 Freescale Semiconductor...
Page 257 The DMMU control register (MD_CTR), shown in Figure 8-7, controls DMMU operation. Field GPM PPM CIDEF WTDEF RS4VD TWAM PPCS — Reset 0000_0 0_0000_0000 Field — DTLB_INDX — Reset 0x0000 Figure 8-7. DMMU Control Register (MD_CTR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-15...
Page 258 8-8, contain the EA to be loaded into a TLB entry Field Reset 0000_0000_0000_0000 Field — — ASID Reset — 787 (MI_EPN); 795 (MD_EPN) Figure 8-8. IMMU/DMMU Effective Page Number Register (M x _EPN) MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-16 Freescale Semiconductor...
Page 259 Access protection group. Up to 16 protection groups supported. Default for ITLB miss is 0 Guarded memory attribute for entry 0 Nonguarded memory (default for ITLB miss) 1 Guarded memory MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-17...
Page 260 8-10, contains the level-two pointer and access protection group of an entry to be loaded into the TLB. Field L2TB Reset — Field L2TB — Reset — Figure 8-10. DMMU Tablewalk Control Register (MD_TWC) MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-18 Freescale Semiconductor...
Page 261 TLB. MI_RPN should be written after MI_EPN and MI_TWC are written. Field Reset — Field Reset — Figure 8-11. IMMU Real Page Number Register (MI_RPN) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-19...
Page 262 Figure 8-12, contains the physical address and the memory attributes of an entry to be loaded into a TLB. This register should be written after the MD_EPN and MD_TWC registers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-20 Freescale Semiconductor...
Page 263 1 16 Kbyte or larger (512 Kbyte or 8 Mbyte) Shared page 0 This entry matches only if the ASID field in the DTLB entry matches the M_CASID value. 1 ASID comparison is disabled for the entry. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-21...
Page 264 EA with the ASID field in the TLB entry when searching for a match. 27 28 Field — CASID Reset — Figure 8-14. MMU Current Address Space ID Register (M_CASID) MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-22 Freescale Semiconductor...
Page 265 MMU Tablewalk Special Register (M_TW) The MMU tablewalk special register (M_TW), shown in Figure 8-16, is a scratch register used by tablewalk exception handlers. Reset — Figure 8-16. MMU Tablewalk Special Register (M_TW) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-23...
Page 266 ASID Address space ID of the DTLB entry to be compared with M_CASID[CASID] Shared page 0 This entry matches only if the ASID field in the DTLB entry matches the value in M_CASID. 1 ASID comparison is disabled for the entry MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-24 Freescale Semiconductor...
Page 267 111 8 Mbyte Cache-inhibit attribute for the entry. 0 Caching is allowed. 1 Caching is inhibited. 24–27 Access protection group. Up to 16 protection groups supported (uses one’s complement format) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-25...
Page 268 1 Subpage 2 (Address[20–21] = 10) User fetch is permitted 0 Subpage 3 (Address[20–21] = 11) User fetch is not permitted 1 Subpage 3 (Address[20–21] = 11) User fetch is permitted MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-26 Freescale Semiconductor...
Page 269 0 Subpage 2 (address[20–21] = 10) is not valid 1 Subpage 2 (address[20–21] = 10) is valid 0 Subpage 3 (address[20–21] = 11) is not valid 1 Subpage 3 (address[20–21] = 11) is valid MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-27...
Page 270 011 512 Kbyte 111 8 Mbyte 23–26 APGI Access protection group inverted. Access protection group number in one’s complement format Guarded memory attribute for the entry 0 Nonguarded memory 1 Guarded memory MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-28 Freescale Semiconductor...
Page 271 Software should take an appropriate action before setting this bit to 1. 1 Changed region. Write access is allowed to this page. Entry valid flag 0 Entry is invalid 1 Entry is valid MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-29...
Page 272 1 Subpage 3 (address[20–21] = 11) User read access is permitted UWP3 0 Subpage 3 (address[20–21] = 11) User write access is not permitted 1 Subpage 3 (address[20–21] = 11) User write access is permitted MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-30 Freescale Semiconductor...
Page 273 The TLB entry is written by loading the tablewalk level-two entry value to Mx_RPN. • A scratch register, M_TW, is provided in addition to the architecture-defined SPRG0–SPRG3, so miss code need not corrupt existing GPRs. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-31...
Page 274 # size into account R1, (R1) # Load level-2 page entry mtspr MI_RPN, R1 # Write TLB entry mfspr R1, M_TW # Restore R1 Figure 8-24. ITLB Reload Code Example MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-32 Freescale Semiconductor...
Page 275 The ASID value in the entry is ignored for the purpose of matching an invalidate address; thus, multiple entries can be invalidated if they have the same effective address and different ASID values. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 8-33...
Page 276 MI_EPN[EV], and writing to the appropriate MD_RPN or MI_RPN. The TLBs are not invalidated automatically on reset, but are disabled. However, they must be invalidated under program control during initialization. MPC885 PowerQUICC Family Reference Manual, Rev. 2 8-34 Freescale Semiconductor...
Page 277 GCLK1 addic mulli addi Fetch Decode addic Read + Execute Bubble addic Writeback addic L Address Drive L Data Load Write Back Figure 9-1. Data Cache Load Timing MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 278 9-4, lwz and xor write back in the same clock since they use the writeback bus in two different ticks (a tick = 1/4 of a processor clock). r12,64 (SP) r5,r5,3 cror 4,14,1 r3,r4.r5 r4,r3,r5 r6,r12.r3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 279 CQ. Here, the CQ is full from executing sub, addic, and and. It takes one more bubble from the load writeback to allow further issue while the CQ retires sub, addic, and and. r12,64 (SP) r5,r5,3 addic r4,r14,1 r3,r4.r5 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 280 Bubble mulli addi Decode addic mulli Read + Execute Bubble Bubble addic mulli Writeback addic L Address Drive L Data Load Writeback Branch Decode Branch Execute Figure 9-7. Branch Folding Timing MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 281 Branch: b, ba, bl, bla, bc, bca, bcl, bcla, bclr, bclrl, Taken 2 bcctr, bcctl Not taken 1 System call: sc, rfi Serialize + 2 — CR logical: crand, crxor, cror, crnand, crnor, crandc, creqv, crorc, mcrf MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 282 Move to/from SPR (Debug, DAR, DSISR): mtspr, mfspr Serialize + 1 String instructions: lswi, lswx, stswi, stswx. See Serialize + 1 + no. of words Section 9.2.2, “String Instruction Latency.” accessed Memory control instructions: isync Serialize MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 283 1 cycle 2 cycles 5 cycles Load/store multiple 1 + N 1 + N ⎛ ⎞ ⎛ ⎞ -------------- -------------- ⎝ ⎠ ⎝ ⎠ N denotes the number of registers transferred. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 284 SPRs.” If the access ends in a bus error, a software emulation exception is taken. All write operations to off-core SPRs (mtspr) are previously synchronized. In other words, the instruction is not taken until all prior instructions terminate. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 285 Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor III-1...
Page 286 Least-significant byte Least-significant bit Load/store unit Memory management unit Most-significant byte Most-significant bit Machine state register Peripheral component interconnect RISC Reduced instruction set computing RTOS Real-time operating system Receive Special-purpose register MPC885 PowerQUICC Family Reference Manual, Rev. 2 III-2 Freescale Semiconductor...
Page 287 Table III-1. Acronyms and Abbreviated Terms (continued) Term Meaning Software watchdog timer Time base register Translation lookaside buffer Transmit MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor III-3...
Page 288 MPC885 PowerQUICC Family Reference Manual, Rev. 2 III-4 Freescale Semiconductor...
Page 289 • Power management • Decrementer • Time base • Periodic interrupt timer (PIT) • External bus interface control • Eight memory banks supported by the memory controller • Debug support MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-1...
Page 290 4,295 seconds (approximately 71.6 minutes). • Freeze support—The SIU determines whether the software watchdog timer, PIT, timebase, and decrementer should continue to run in freeze mode. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-2 Freescale Semiconductor...
Page 291 PCMCIA bank mapped to slot B, CS7/CE2_B is asserted. WE0/BS_AB0/IORD Dynamically active depending on the machine (GPCM, UPMB, or PCMCIA WE1/BS_AB1/IOWR interface) assigned to control the required slave. WE2/BS_AB2/PCOE WE3/BS_AB3/PCWE MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-3...
Page 292 MASKNUM are mask-programmed and cannot be changed. Field Reset Set by reset configuration Field PARTNUM MASKNUM Reset 000_0000 Value depends on the mask revision Figure 10-2. Internal Memory Map Register (IMMR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-4 Freescale Semiconductor...
Page 293 (IMMR & 0xFFFF0000) + 0x000 Field — MPRE MLRC AEME SEME BSC GB5E B2DD B3DD — Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x002 Figure 10-3. SIU Module Configuration Register (SIUMCR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-5...
Page 294 If AEME = 1, the memory controller interprets any assertion of AS as an external asynchronous master initiating a transaction. If it is reset, the memory controller ignores the value of AS. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-6 Freescale Semiconductor...
Page 295 HRESET but not by SRESET. Field SWTC Reset 1111_1111_1111_1111 (IMMR & 0xFFFF0000) + 0x004 Field — SWF SWE SWRI SWP Reset 1111_1111 (IMMR & 0xFFFF0000) + 0x006 Figure 10-4. System Protection Control Register (SYPCR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-7...
Page 296 Canceled speculative accesses that do not cause an interrupt may set these bits. TESR has two identical sets of fields, one for instruction transfers and one for data transfers.This register is affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-8 Freescale Semiconductor...
Page 297 Table 10-6. Table 10-6. Key Registers Offset Name Size System Integration Timers Keys 0x300 TBSCRK—Timebase status and control register key 32 bits 0x304 TBREFAK—Timebase reference register A key 32 bits MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-9...
Page 298 TBK. A write to the timebase register when it is locked results in a software emulation exception. Reads are allowed at all times to any of the SIU registers, regardless of whether they are locked or unlocked. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-10 Freescale Semiconductor...
Page 299 (SIUMCR).” 10.5.1 Interrupt Structure The SIU receives interrupts from internal sources, like the PIT, communications processor module (CPM), and the external IRQ pins. Figure 10-7 shows the MPC885 interrupt structure. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-11...
Page 300 Asserting IRQ0 causes an NMI. The other 15 interrupt sources assert a single interrupt request to the core (the external interrupt). Table 10-7 shows interrupt priorities. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-12 Freescale Semiconductor...
Page 301 SIU interrupt processing. Start SIU interrupt occurs Set bit in SIPEND Bit set in SIMASK Bit not set in SIMASK Assert external interrupt to core Figure 10-8. SIU Interrupt Processing MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-13...
Page 302 The SIU’s interrupt controller includes the SIU interrupt pending register (SIPEND), SIU interrupt mask register (SIMASK), SIU interrupt edge/level register (SIEL), and SIU interrupt vector register (SIVEC) registers. These are described in the following sections. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-14 Freescale Semiconductor...
Page 303 Note that IRQ0 can be masked in only a very limited sense. If SIEL[ED0] = 1, edge-sensitive, and SIPEND[IRQ0] is not cleared in the interrupt service routine, further assertions of IRQ0 are masked. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-15...
Page 304 2. Modify the mask register. 3. Set MSR[EE]. (Enable external interrupts to the core.) This mask modification procedure ensures that an already pending interrupt is not masked before being serviced. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-16 Freescale Semiconductor...
Page 305 — Reserved, should be cleared. 10.5.4.4 SIU Interrupt Vector Register (SIVEC) The SIU interrupt vector register (SIVEC) is shown in Figure 10-13. This register is affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-17...
Page 306 4, which allows indexing into the table. When read as a half word, each entry can contain a full routine of up to 256 instructions; see Figure 10-14 Table 10-7. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-18 Freescale Semiconductor...
Page 307 The maximum value is 2,040 system clocks. The bus monitor is always active when FRZ is asserted or when a debug mode request is pending, regardless of the state of the SYPCR[BME] bit. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-19...
Page 308 SWTC, the software watchdog timer is not updated until the servicing sequence is written to SWSR. If the SWE bit is loaded with a zero, the modulus counter will not count. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-20 Freescale Semiconductor...
Page 309 SWSR fields. Table 10-13. SWSR Field Descriptions Bits Name Description 0–15 Sequence. This field is the pattern that is used to control the state of the software watchdog timer. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-21...
Page 310 Control of the decrementer is provided in the TBSCR. The decrementer and timebase use TMBCLK. Note that DEC is a keyed register. It must be unlocked in TBK before it can be written. Field Reset — Figure 10-18. Decrementer Register (DEC) MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-22 Freescale Semiconductor...
Page 311 Table 10-16 describes TBU fields. Table 10-16. TBU Field Descriptions Bits Name Description 0–31 Timebase upper. The value in this field is used as an upper part of the timebase counter. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-23...
Page 312 Table 10-18. TBREFA/TBREFB Field Descriptions Bits Name Description 0–31 TBREFA Timebase reference A. Represents the 32-bit reference value for TBL. 0–31 TBREFB Timebase reference B. Represents the 32-bit reference value for TBL MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-24 Freescale Semiconductor...
Page 313 PS is cleared. If PS is set again, before being cleared, the interrupt remains pending until PS is cleared. Any write to PITC stops the current countdown MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-25...
Page 314 Periodic interrupt status. Can be cleared by writing a 1 to it (zero has no effect). 0 The PIT is unaffected. 1 The PIT has issued an interrupt. 9–12 — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-26 Freescale Semiconductor...
Page 315 Bits Name Description 0–15 PITC PIT count. Contains the count for the periodic timer. Setting this field to 0xFFFF selects the maximum count period. 16–31 — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 10-27...
Page 316 This is controlled by the associated bits in the control register of each timer. If they are programmed to stop counting when FRZ is asserted, the counters maintain their values until FRZ is negated. The bus monitor, however, will be enabled regardless of this signal’s state. MPC885 PowerQUICC Family Reference Manual, Rev. 2 10-28 Freescale Semiconductor...
Page 317 The MPC885 has several sources of input to the reset logic: • Power-on reset • External hard reset • Internal hard reset — Software watchdog reset — Checkstop reset — Debug port hard reset • JTAG reset MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 11-1...
Page 318 HRESET and SRESET high. See Section 11.3.1, “Hard Reset,” for more information. The causes of internal hard reset are as follows: • Software watchdog reset • Checkstop reset • Debug port hard reset MPC885 PowerQUICC Family Reference Manual, Rev. 2 11-2 Freescale Semiconductor...
Page 319 • Wait for 16 clocks 16 Clocks Expire • Test for HRESET or SRESET Start Normal Operation (From system reset interrupt exception vector) Figure 11-1. Power-On and Hard Reset Sequence MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 11-3...
Page 320 The 32-bit reset status register (RSR) is memory-mapped into the MPC885 system interface unit register map and receives its default reset values at power-on reset. This register is also affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 11-4 Freescale Semiconductor...
Page 321 Debug port soft reset status. Cleared by a power-on reset. When the debug port soft reset request is set, DBSRS is set and remains set until software clears it. 0 No debug port soft reset request occurred. 1 A debug port soft reset request occurred. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 11-5...
Page 322: Hard Reset
Configuration Word DX (Data Line) MPC885 MPC860 HRESET RSTCONF NOTE: The value of the internal pull-down resistor is not specified or guaranteed. Figure 11-4. Data Bus Configuration Input Circuit MPC885 PowerQUICC Family Reference Manual, Rev. 2 11-6 Freescale Semiconductor...
Page 323 Figure 11-6 shows a reset operation with a long PORESET signal assertion. CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] Default RSTCONF Controlled Figure 11-6. Reset Configuration Sampling for Long PORESET Assertion MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 11-7...
Page 324 Initial interrupt prefix. Defines the initial value of the MSR[IP] which defines the interrupt table location. If IIP is cleared (default), the MSR[IP] initial value is one; if it is set, the MSR[IP] initial value is zero. See Section 4.1.2.3.1, “Machine State Register (MSR).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 11-8 Freescale Semiconductor...
Page 325 DBGC = 10 DBGC = 11 IP_B[0–1]/IWP[0–1]/VFLS[0–1] IP_B[0–1] IWP[0–1] Reserved VFLS[0–1] IP_B3/IWP2/VF2 IP_B3 IWP2 IP_B4/LWP0/VF0 IP_B4 LWP0 IP_B5/LWP1/VF1 IP_B5 LWP1 OP2/MODCK1/STS ALE_B/DSCK/AT1 ALE_B IP_B2/IOIS16_B/AT2 IP_B2 IP_B6/DSDI/AT0 IP_B6 IP_B7/PTR/AT3 IP_B7 OP3/MODCK2/DSDO MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 11-9...
Page 326: Soft Reset
Note the following when connecting the TRST (test reset) signal: • If TAP is never used, connect TRST to ground. • If TAP is used, connect TRST to PORESET. See also Section 54.6, “Recommended TAP Configuration.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 11-10 Freescale Semiconductor...
Page 327 This section lists additional reading that provides background for the information in this manual. MPC8xx Documentation Supporting documentation for the MPC885 can be accessed through the world-wide web at http://www.freescale.com. This documentation includes technical specifications, reference materials, and detailed applications notes. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor IV-1...
Page 328 Built-in self test Basic rate interface BUID Bus unit ID Content-addressable memory Communications processor module Cyclic redundancy check Direct memory access DPLL Digital phase-locked loop DRAM Dynamic random access memory MPC885 PowerQUICC Family Reference Manual, Rev. 2 IV-2 Freescale Semiconductor...
Page 329 Peripheral component interconnect PCMCIA Personal Computer Memory Card International Association Primary rate interface Receive Serial communications controller Serial control port SDLC Synchronous data link control SDMA Serial DMA Serial interface MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor IV-3...
Page 330 Special-purpose register SRAM Static random access memory Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter MPC885 PowerQUICC Family Reference Manual, Rev. 2 IV-4 Freescale Semiconductor...
Page 331 MPC885/MPC880 Signals The following sections describe the signals, pin numbers, and signal descriptions. 12.1.1 MPC885/MPC880 Signals and Pin Numbers Figure 12-1 Figure 12-2 show the MPC885 signals and pin numbers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-1...
Page 332 1–W4 SMSYN1/MII2-TXD2 SOC/CLK7/TIN4/PD3 1–T9 T7–1 PE16/L1RCLKB/CLK6/TXD3/ 1–V18 MII2-TXCLK/RMII2-REFCLK DSDI/TDI 1–T16 PE15/TGATE1/MII2-TXD1/RMII2-TXD1 W6–1 DSCK/TCK 1–U17 PE14/RXD3/MII2-TXD0/RMII2-TXD0 V7–1 TRST 1–W18 DSDO/TDO 1–T17 1–D7 Figure 12-1. MPC885 Signals and Pin Numbers (Part 1) MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-2 Freescale Semiconductor...
Page 333 A10–1 IP_B5/LWP1/VF1 T5-1 MII1_TXEN A8–1 IP_B6/DSDI/AT0 B8–1 IP_B7/PTR/AT3 B6-–OP0/UtpClk_Split B6, C6–2 C6–OP1 D6–1 OP2/MODCK1/STS A6–1 OP3/MODCK2/DSDO A7–1 BADDR30/REG C5, B5–2 BADDR[28:29] Figure 12-2. MPC885 Signals and Pin Numbers (Part 2) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-3...
Page 334 The MPC885 samples TS when it is not the external bus master to allow the memory controller/PCMCIA interface to control the accessed slave device. It indicates that an external synchronous master initiated a transaction. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-4 Freescale Semiconductor...
Page 335 MPC885 and all other devices. The 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers. D0 is the msb of the data bus. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-5...
Page 336 BR7 and OR7 in the memory controller. Card Enable 2 Slot B—Output that enables odd byte transfers when accesses to the PCMCIA slot B are handled under the control of the PCMCIA interface. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-6 Freescale Semiconductor...
Page 337 UPMA, as programmed by the user. For read or writes, asserted only if their corresponding data lanes contain valid data: BS_A0 for D[0:7], BS_A1 for D[8:15], BS_A2 for D[16:23], BS_A3 for D[24:31] MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-7...
Page 338 When RSTCONF is negated, the MPC885 uses the default configuration mode. Note that the initial base address of internal registers is determined in this sequence. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-8 Freescale Semiconductor...
Page 339 Input Port A 1—This input signal is monitored by the MPC885 and its value is reflected in the PIPR and PSCR of the PCMCIA UTPB_Split[1] interface. UTPB_Split[1]—This input signal is used as Rx data in split bus mode only. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-9...
Page 340 When the transaction is initiated by the core, it indicates if the transfer is for user or supervisor state. This signal is not used for transactions initiated by external masters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-10 Freescale Semiconductor...
Page 341 Visible Instruction Queue Flushes Status—The MPC885 outputs VF1 with VF0 and VF2 when instruction flow tracking is required. VF n reports the number of instructions flushed from the instruction queue in the core. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-11...
Page 342 PGCRB register in the PCMCIA interface. DSDO Mode Clock 2—This input is sampled at the PORESET negation to configure the PLL/clock mode of operation. Development Serial Data Output—Output data from the debug port interface. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-12 Freescale Semiconductor...
Page 343 I/O port A RXD2—Receive data input for SCC2 PA[12] Hi-Z Bidirectional General-Purpose I/O Port A Bit 12—Bit 12 of the general-purpose TXD2 (optional: I/O port A open-drain) TXD2—Transmit data output for SCC2 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-13...
Page 344 Bidirectional General-Purpose I/O Port A Bit 4—Bit 4 of the general-purpose CTS4 I/O port A MII1-TXD1 CTS4—Clear to send modem line for SCC4 RMII1-TXD1 MII1-TXD1—Media-independent interface 1, transmit data 1 RMII1-TXD1—Reduced media-independent interface 1, transmit data 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-14 Freescale Semiconductor...
Page 345 General-Purpose I/O Port B Bit 27—Bit 27 of the general-purpose I2CSDA (optional: I/O port B BRGO1 open-drain) I2CSDA—I C serial data pin. Bidirectional; should be configured as an open-drain output BRGO1—BRG1 output clock MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-15...
Page 346 PHSEL[0]—Most significant bit of PHY select bus (used in classic RXADDR0 SAR MPHY mode only) UTOPIA multi-PHY transmit address line 0 - only if in ESAR mode UTOPIA multi-PHY receive address line 0 MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-16 Freescale Semiconductor...
Page 347 RTS3—Request to send modem line for SCC3 TXCLAV L1ST1—One of four output strobes that can be generated by the RXCLAV serial interface TXCLAV—Transmit cell available input signal RXCLAV—Receive cell available input signal MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-17...
Page 348 L1TSYNCA—Transmit sync input for serial interface TDMa SDACK2—SDMA acknowledge 1 output that is used as a peripheral interface signal for IDMA emulation or as a CAM interface signal for Ethernet MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-18 Freescale Semiconductor...
Page 349 Bidirectional General-Purpose I/O Port D Bit 8—Bit 8 of the general-purpose RXD4 I/O port D MII-MDC RXD4—Receive data for serial channel 4 MII-MDC—Media-independent interface management data RMII-MDC clock. RMII-MDC—Reduced media-independent interface management data clock. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-19...
Page 350 MII2-CRS (optional: MII2-CRS —Media-independent interface 2, carrier receive open-drain) sense PE28 Hi-Z Bidirectional General-Purpose I/O Port E Bit 28 TOUT3 (optional: TOUT3—Timer 3 output MII2-COL open-drain) MII2-COL—Media-independent interface 2 collision MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-20 Freescale Semiconductor...
Page 351 L1RSYNCA (optional: L1RSYNCA—Receive sync input for serial interface TDMa SMTXD2 open-drain) SMTXD2—SMC2 transmit data output CTS3 CTS3—Clear to send modem line for SCC3 MII2-TXER MII2-TXER—Media independent interface 2, transmit error MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-21...
Page 352 Test reset for the JTAG scan chain logic MII1_CRS Hi-Z Input MII1_CRS —Media-independent interface 1, carrier receive sense MII_MDIO Hi-Z Bidirectional MII_MDIO—Media-independent interface management data MII1_TXEN Output MII1_TXEN—Media-independent interface 1, transmit enable MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-22 Freescale Semiconductor...
Page 353 12.2 MPC875/MPC870 Signals The following sections describe the signals, their descriptions, and pin numbers. 12.2.1 MPC875/MPC870 Signals and Pin Numbers Figure 12-3 Figure 12-4 show MPC875 signals and pin numbers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-23...
Page 354 1–R6 SMTXD1/MII2-TXD3/PE18 1–M5 SMSYN1/TIN3/CLK5/BRG03/MII2-TXD2/PE17 1–T8 L1RCLKB/CLK6/MII2-TXCLK/RMII2-REFCLK/PE16 1–U6 TGATE1/MII2-TXD1/RMII2-TXD1/PE15 1–T7 RXD3/MII2-TXD0/RMII2-TXD0/PE14 1–P8 1–T14 DSDI/TDI 1–T13 DSCK/TCK 1–R13 TRST 1–U14 DSDO/TDO 1–P13 1–C7 Figure 12-3. MPC875 Signals and Pin Numbers (Part 1) MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-24 Freescale Semiconductor...
Page 355 U10-1 F4–IP_A6 C2–IP_A7 MII1_COL R10-1 MII_MDIO M13-1 U5-1 MII1_TXEN B6-–OP0/ B6, C6–2 C6–OP1 B5–1 OP2/MODCK1/STS B2–1 OP3/MODCK2/DSDO D8–1 BADDR30/REG E8,C5–2 BADDR[28:29] Figure 12-4. MPC875 Signals and Pin Numbers (Part 2) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-25...
Page 356 The MPC875 samples TS when it is not the external bus master to allow the memory controller/PCMCIA interface to control the accessed slave device. It indicates that an external synchronous master initiated a transaction. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-26 Freescale Semiconductor...
Page 357 MPC875 and all other devices. The 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers. D0 is the msb of the data bus. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-27...
Page 358 BR7 and OR7 in the memory controller. Card Enable 2 Slot B—This output enables odd byte transfers when accesses to the PCMCIA slot B are handled under the control of the PCMCIA interface. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-28 Freescale Semiconductor...
Page 359 UPMA, as programmed by the user. For read or writes, asserted only if their corresponding data lanes contain valid data: BS_A0 for D[0:7], BS_A1 for D[8:15], BS_A2 for D[16:23], BS_A3 for D[24:31] MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-29...
Page 360 When RSTCONF is negated, the MPC875 uses the default configuration mode. Note that the initial base address of internal registers is determined in this sequence. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-30 Freescale Semiconductor...
Page 361 PCMCIA space. IP_A3 Hi-Z Input Input Port A 3—This input signal is monitored by the MPC875 and its value is reflected in the PIPR and PSCR of the PCMCIA interface. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-31...
Page 362 PGCRB register in the PCMCIA interface. DSDO Mode Clock 2—This input is sampled at the PORESET negation to configure the PLL/clock mode of operation. Development Serial Data Output—Output data from the debug port interface. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-32 Freescale Semiconductor...
Page 363 General-Purpose I/O Port A Bit 11—Bit 11 of the general-purpose RXD4 (optional: I/O port A. MII1-TXD0 open-drain) RXD4—Receive data input for SCC4. RMII1-TXDO MII1-TXD0—Media independent interface 1, transmit data 0. RMII1-TXD0—Reduced media-independent interface 1, transmit data 0. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-33...
Page 364 Bidirectional General-Purpose I/O Port A Bit 0—Bit 0 of the general-purpose MII1-RXD1 I/O port A. RMII1-RXD1 MII1-RXD1 —Media-independent interface 1, receive data 1. TOUT4 RMII1-RXD1—Reduced media-independent interface 1, receive data 1. TOUT4—Timer 4 output. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-34 Freescale Semiconductor...
Page 365 General-Purpose I/O Port B Bit 19—Bit 19 of the general-purpose RTS4 (optional: I/O port B. MII1-RXD3 open-drain) RTS4—Request to send modem line for SCC4. MII1-RXD3 —Media-independent interface 1, receive data 3. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-35...
Page 366 MII-RXCLK—Media-independent interface receive clock PE30 Hi-Z Bidirectional General-Purpose I/O Port E Bit 30 L1RXDB (optional: L1RXDB—Receive data input for the serial interface TDMb. MII1-RXD2 open-drain) MII1-RXD2 —Media-independent interface 1, receive data 2. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-36 Freescale Semiconductor...
Page 367 MII2-RXD0—Media-independent interface 2, receive data 0. RMII2-RXD0 RMII2-RXD0—Reduced media-independent interface 2, receive data 0. PE20 Hi-Z Bidirectional General-Purpose I/O Port E Bit 20 MII2-TXER (optional: MII2-TXER - Media independent interface 2, transmit error. open-drain) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-37...
Page 368 Test reset for the JTAG scan chain logic MII1_CRS Hi-Z Input MII1_CRS —Media-independent interface 1, carrier receive sense MII_MDIO Hi-Z Bidirectional MII_MDIO —Media-independent interface management data MII1_TXEN Output MII1_TXEN —Media-independent interface 1, transmit enable MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-38 Freescale Semiconductor...
Page 369 Section 11.3.1.1, “Hard Reset Configuration Word.” When HRESET (or PORESET) is asserted, these pins immediately begin functioning as the signals selected in the SIUMCR. The behavior of these signals is shown in Table 12-3. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-39...
Page 370 Due to the behavior of the buffer when being driven high, a pull-up resistor is required externally to function as a ‘bus keep’ for these shared signals in periods when no drivers are active and to keep the buffer MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-40 Freescale Semiconductor...
Page 371 TA after 15 cycles. If external logic drives TA before 14 clocks have elapsed then the TA is accepted by the processor as a cycle termination.) • For UPM-controlled chip-selects, the TA buffer is enabled as an output throughout the entire bus cycle. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-41...
Page 372: Reset Configuration
12.6.1.1 Bus Control Signals and Interrupts Signals with open-drain buffers and active pull-up buffers (HRESET, SRESET, TEA, TS, TA, BI, and BB) must have external pull-up resistors. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-42 Freescale Semiconductor...
Page 373: Unused Outputs
However, unused pins of port A, B, C, or D can be configured as outputs, and, if they are configured as outputs they do not require external terminations. 12.6.4 Unused Outputs Unused outputs can be left unterminated. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 12-43...
Page 374 Memory controller aborts the current access, and signals drive to their inactive state (high). Refresh continues. Port I/O signals are not reconfigured (maintain previous programming). SIU pin configuration maintains previous programming; see Table 12-3. MPC885 PowerQUICC Family Reference Manual, Rev. 2 12-44 Freescale Semiconductor...
Page 375 13-1, around the rising clock edge. To ensure that an input signal is recognized on a specific rising clock edge, that input must be stable during the sample window. If an input changes during the window, MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-1...
Page 376 These signals are valid at the rising edge of the clock in which the transfer start signal (TS) is asserted. 13.3 Bus Interface Signal Descriptions Figure 13-3 shows the bus signals for the MPC885. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-2 Freescale Semiconductor...
Page 377 Driven low indicates that a write access is in progress. Sampled by the MPC885 when an external device initiates a transaction and the memory controller was configured to handle external master accesses. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-3...
Page 378 See Retry Section 13.4.9, “Memory Reservation.” For regular transactions, the slave device drives this signal to indicate that the MPC885 must relinquish the bus and retry the cycle. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-4 Freescale Semiconductor...
Page 379 Qualified BG = BG & ~BB When the internal arbiter is disabled, BG is sampled and properly qualified by the MPC885 when an external bus transaction is to be executed by the chip. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-5...
Page 380 The master must consider the one dead clock cycle switching between drivers to avoid electrical contention. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-6 Freescale Semiconductor...
Page 381 Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Receives Address Returns data Asserts Transfer Acknowledge (TA) Receives data Figure 13-4. Basic Flow Diagram of a Single-Beat Read Cycle MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-7...
Page 382 Receive BG and BB negated Assert BB, drive address and assert TS A[0:31] TSIZ[0:1], AT[0:3] BURST Data Data is Valid Figure 13-5. Basic Timing: Single-Beat Read Cycle, Zero Wait States MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-8 Freescale Semiconductor...
Page 383 Receive BG and BB negated Assert BB, drive address and assert TS A[0:31] TSIZ[0:1], AT[0:3] BURST Data Wait State Data is Valid Figure 13-6. Basic Timing: Single-Beat Read Cycle, One Wait State MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-9...
Page 384 Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives data Asserts Transfer Acknowledge (TA) Interrupts data driving Figure 13-7. Basic Flow of a Single-Beat Write Cycle MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-10 Freescale Semiconductor...
Page 385 Receive BG and BB negated Assert BB, drive address and assert TS A[0:31] TSIZ[0:1], AT[0:3] BURST Data Data is sampled Figure 13-8. Basic Timing: Single-Beat Write Cycle, Zero Wait States MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-11...
Page 386 13-10, the MPC885 provides an effective mechanism for interfacing with 16- and 8-bit port size memories by allowing transfers to these devices when they are controlled by the internal memory controller. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-12 Freescale Semiconductor...
Page 387 External Bus Interface CLKOUT A + 2 A[0:31] TSIZ[0:1] BURST Data ABCDEFGH EFGHEFGH Figure 13-10. Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-13...
Page 388 MPC885 system should attempt only 16-byte burst transfers except for external masters with a dedicated chip select, such as an external MPC603 that bursts to a chip select programmed for a 32-byte burst. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-14 Freescale Semiconductor...
Page 389 2 → data 3 → data 4 →..→ data 7 → data 0 → data 1 The following flow, Figure 13-11, and timing diagrams, Figure 13-12 through Figure 13-15, show the handshakes for burst read transactions. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-15...
Page 390 Negates Burst Data in Progress (BDIP) Don’t drive data Returns data Asserts Transfer Acknowledge (TA) Receives data BDIP asserted Don’t drive data Figure 13-11. Basic Flow of a Burst-Read Cycle MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-16 Freescale Semiconductor...
Page 391 BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Figure 13-12. Burst-Read Cycle: 32-Bit Port Size, Zero Wait State MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-17...
Page 392 Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 13-13. Burst-Read Cycle: 32-Bit Port Size, One Wait State MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-18 Freescale Semiconductor...
Page 393 Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 13-14. Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-19...
Page 394 Figure 13-15. Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats The following flow, Figure 13-16, and timing diagram, Figure 13-17, show the handshakes for a burst write transaction. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-20 Freescale Semiconductor...
Page 395 Negates Burst Data in Progress (BDIP) Don’t sample next data Asserts Transfer Acknowledge (TA) Stops driving data BDIP asserted Don’t sample next data Figure 13-16. Basic Flow of a Burst Write Cycle MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-21...
Page 396 (BI). The MPC885 responds by terminating the burst and accessing the rest of the 16-byte block, using three single-beat read cycles. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-22 Freescale Semiconductor...
Page 397 Byte access can have any address alignment • Half-word access must have A[31] = 0b0 • Word access must have A[30:31] = 0b00 • For burst accesses A[30:31] = 0b00 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-23...
Page 398 Interface Output Register D[0:7] D[8:15] D[16:23] D[24:31] 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Figure 13-20. Interface to Different Port Size Devices MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-24 Freescale Semiconductor...
Page 399 BR and waits for the arbiter to assert BG. The new master must look at BB to ensure that no other master is driving the bus before it can assert BB to assume bus mastership. (Note that the internal MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-25...
Page 400 BR is negated or it can remain asserted to park the current master on the bus. The internal arbiter may take away the BG if the new master does not assert BB within one clock. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-26 Freescale Semiconductor...
Page 401 BB, regardless of how many cycles have passed since the previous master relinquished the bus. See Figure 13-22. External Bus Master MPC885 Slave 2 Figure 13-22. Bus Busy (BB) and Transfer Start (TS) Connection Example MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-27...
Page 402 MPC885 does not require it, or the external device has higher priority than the current internal bus master, the MPC885 grants the bus to the external device. Figure 13-24 shows the internal finite state machine that implements the arbiter protocol. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-28 Freescale Semiconductor...
Page 403 TS to avoid having a slave recognize this signal as asserted when no master drives it; see Figure 13-22. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-29...
Page 404 These types are designated as either a normal/alternate master cycle, user/supervisor (problem/privilege), and instruction/data types. The address type signals are valid at the rising edge of the clock in which the special transfer start (STS) signal is asserted. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-30 Freescale Semiconductor...
Page 405 Core-initiated, normal instruction, user mode Core-initiated, reservation data, user mode Core-initiated, normal data, user mode DMA-initiated, normal, AT[1:3] user-programmable (see IDMA and DMA function code registers) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-31...
Page 406 (for a data cycle). These indications can also be monitored on two separate signals (PTR and RSV), if desired. • PTR is low when the following is true: — AT0 = 0 (Core access) — AT2 = 0 (Instruction) — AT3 = 0 (Program Trace) MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-32 Freescale Semiconductor...
Page 407 This indicates that termination signals should be connected to power through a pull-up resistor to prevent a master from sampling undefined values in any of these signals when no real slave is addressed. Figure 13-25 Figure 13-26. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-33...
Page 408 Slave 2 Slave 2 allowed to negates allowed to negates drive acknowledge drive acknowledge acknowledge signals acknowledge signals signals signals ‘turns off’ ‘turns off’ Figure 13-26. Termination Signals Protocol Timing Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-34 Freescale Semiconductor...
Page 409 Holds one reservation for each local master capable of memory reservations. • Sets the reservation when that master issues a load and reserve request. • Clears the reservation when another master issues a store to the reservation address. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-35...
Page 410 KR on an intermediate beat may result in erratic operation, including lockup of the MPC885 requiring hard reset. Figure 13-28 shows the reservation protocol for a multi-level (local) bus. The system describes a situation in which the reserved location is in the remote bus. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-36 Freescale Semiconductor...
Page 411 TA is asserted. When TEA is sampled as asserted, it should be negated before the next rising edge to avoid influencing the next initiated bus cycle. TEA is an open-drain pin that allows the wire-OR of different sources of error generation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-37...
Page 412 If the external master does not use the bus, the MPC885 initiates a new transfer with the same address and attributes as before. CLKOUT BG (Output) Allow external master to gain the bus A[0:31] TSIZ[0:1] BURST Data RETRY Figure 13-29. Retry Transfer Timing–Internal Arbiter MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-38 Freescale Semiconductor...
Page 413 RETRY is detected asserted, BR and BB are negated together. Normal arbitration resumes one clock cycle later. CLKOUT BR (Output) Allow external master to gain the bus A[0:31] TSIZ[0:1] BURST Data RETRY Figure 13-30. Retry Transfer Timing–External Arbiter MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-39...
Page 414 TA, then subsequent single-beat transfers, which are initiated by the MPC885 to complete the access, process the RETRY assertion as a TEA. MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-40 Freescale Semiconductor...
Page 415 MPC885 recognizes the termination signals provided by the slave device that is addressed by the initiated transfer. Table 13-6. Termination Signals Protocol RETRY/KR Action Transfer error termination Normal transfer termination Retry transfer termination/kill reservation MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 13-41...
Page 416 External Bus Interface MPC885 PowerQUICC Family Reference Manual, Rev. 2 13-42 Freescale Semiconductor...
Page 417 Contains digital system PLL (DPLL) • Supports crystal oscillator circuits • Clock dividers are provided for internal clocks • Contains the following power modes — Normal High — Normal Low MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-1...
Page 418 XTAL Main and Driver OSCM Clock ÷512 EXTAL Oscillator Note that only CLKOUT is an actual external output; all other outputs are internal signals. Figure 14-1. Clock Source and Distribution MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-2 Freescale Semiconductor...
Page 419 Section 14.6.1, “System Clock and Reset Control Register (SCCR).” For more information, see Section 14.2.3, “DPLL Reset Configuration,” Section 14.3.2, “PIT Clock (PITCLK),” Section 14.3.3, “Time Base and Decrementer Clock (TMBCLK).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-3...
Page 420 EXTCLK is aligned (locked/synchronized) with the rising edge of CLKOUT. For a non integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew. MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-4 Freescale Semiconductor...
Page 421 (MFI), the numerator part (MFN), the denominator part minus 1(MFD), and the predivison factor minus 1 (PDF) with their ranges listed in Table 14-9. The total MF value, MFI+(MFN/(MFD+1)), must be between 5 to 15. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-5...
Page 422 Table 14-3. After PORESET is negated, the MODCK[1:2] values are internally latched, and the signals applied to MODCK[1:2] can be changed. MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-6 Freescale Semiconductor...
Page 423 This risk should be taken into account when MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-7...
Page 424: Clock Signals
Clock out is an external clock signal used to drive other devices, and thus provide the ability to operate synchronously with those devices. Equivalent to the internal GCLK2_50 signal. TMBCLK Clocks the time base and decrementer PITCLK Clocks the periodic interrupt timer MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-8 Freescale Semiconductor...
Page 425 DFBRG CPM and GCLK1C (Refresh Timers) GCLK2C Phase GCLK2 DFNH Timer module, GCLK1 Core, CPM and SIU. GCLK1_50 DFNL EBDF Phase UPM and SIU GCLK2_50 CLKOUT Figure 14-4. Clock Dividers MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-9...
Page 426 When GCLKx is divided, its duty cycle is modified. One phase remains the same while the other stretches out. GCLKx no longer has a 50% duty cycle when the division factor is greater than 1, as shown in Figure 14-6. MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-10 Freescale Semiconductor...
Page 427 Figure 14-7. GCLK1 GCLK2 GCLK1_50 (EBDF=00) GCLK2_50 (EBDF=00) CLKOUT (EBDF=00) GCLK1_50 (EBDF=01) GCLK2_50 (EBDF=01) CLKOUT (EBDF=01) Figure 14-7. Memory Controller and External Bus Clocks Timing Diagram for EBDF=0 and EBDF=1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-11...
Page 428 CLKOUT is the only externally visible clock, and is equivalent to the internal signal GCLK2_50. While the DPLL is acquiring lock, the CLKOUT signal does not oscillate and remains in a low state. MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-12 Freescale Semiconductor...
Page 429 The signal synchronization circuitry is used to sample and synchronize asynchronous external signals provided to these ports. SYNCCLK allows the serial interface, serial communication controller, and serial MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-13...
Page 430 Note: Since OSCM just uses one frequency input of 10 MHz, it is not possible to get a PITCLK period of 1 second. This could however be achieved by giving an appropriate input to the EXTCLK. MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-14 Freescale Semiconductor...
Page 431 Clock Drivers DEC, SCCR, PLPRCR, and RSR Analog Clock Control DPLL and Digital DPLL V DDH 3.3 V V DDL V DDSYN 1.8 V 1.8 V Figure 14-11. MPC885 Power Rails MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-15...
Page 432 VDDSYN plane implemented as an island in the VDDL power plane, connected to the VDDL power plane with an inductor and to the ground plane with MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-16 Freescale Semiconductor...
Page 433 Normal low mode can be entered at any time, and the frequency of operation of normal low mode can be changed dynamically. This is controlled by PLPRCR[CSRC] and SCCR[DFNL]. Changes to these bits take effect immediately. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-17...
Page 434 * PTDIV depends on the combination of MODCK1 and MODCK2. PTSEL depends on MODCK1. See Table 14-5 more information. † This field is set according to the default of the hard reset configuration word. Figure 14-12. System Clock and Reset Control Register (SCCR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-18 Freescale Semiconductor...
Page 435 Section 11.3.1.1, “Hard Reset Configuration Word.” 00 CLKOUT is GCLK2 divided by 1. 01 CLKOUT is GCLK2 divided by 2. 10 Reserved. 11 Reserved. 15–16 — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-19...
Page 436 011 Divide by 8. 100 Divide by 16. 101 Divide by 32. 110 Divide by 64. 111 Reserved. 27–29 DFUTP UTOPIA clock dividers; see Section 42.2, “UTOPIA Mode Registers.” 30–31 DFAUTP MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-20 Freescale Semiconductor...
Page 437 Selection Bits for the Divider after the Double Clock (fdck) 00 Divide By 1 01 Divide By 2 10 Divide By 4 11 = Reserved. Refer to Section 14.2.2, “Digital Phase Lock Loop and Interface.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-21...
Page 438 1 Second Order (should be used when fractional part, MFN/MFD, in undivisible form is less than 1/10) This bit is ignored if the MFN is zero. The total multiplication factor, including both the integer and fractional parts, must be between 5 to 15. MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-22 Freescale Semiconductor...
Page 439 PLPRCR[CSR] and DER[CHSTPE] bit combinations. Table 14-10. PLPRCR[CSR] and DER[CHSTPE] Bit Combinations PLPRCR[CSR] DER[CHSTPE] Checkstop Mode Result — — — Enter debug mode — Automatic reset — Enter debug mode MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 14-23...
Page 440 Clocks and Power Control MPC885 PowerQUICC Family Reference Manual, Rev. 2 14-24 Freescale Semiconductor...
Page 441 — Address types protection for memory bank accesses by internal masters — Control signal generation machine selection on a per-bank basis — Support for external master access to memory banks — Synchronous and asynchronous external masters support MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-1...
Page 442 — Internal address multiplexing for all on-chip bus masters supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks — Glueless interface to EDO, self refresh, and synchronous DRAM devices MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-2 Freescale Semiconductor...
Page 443 UPM Command Done Memory Command Register (MCR) Memory Data Register (MDR) Memory Status Register (MSTAT) Memory Address Register (MAR) Memory Periodic Timer Prescale Register (MPTPR) Figure 15-1. Memory Controller Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-3...
Page 444 The memory controller functionality minimizes the need for glue logic in MPC885-based systems. In Figure 15-3, CS0 is used with the 16-bit boot EPROM with BR0[MS] defaulting to select the GPCM. CS1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-4 Freescale Semiconductor...
Page 445 At every clock cycle, the logical value of the external signals specified in the RAM array is output on the corresponding UPM pins. See Figure 15-4. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-5...
Page 446 Memory command register (MCR) √ Machine A mode register (MAMR) √ Machine B mode register (MBMR) √ Memory data register (MDR) √ Memory address register (MAR) √ Memory periodic timer prescaler register (MPTPR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-6 Freescale Semiconductor...
Page 447 Half Words Predefined Words (on Word Port Size Boundaries) Even Even √ √ 8-bit — — — √ √ √ (on D[0:15]) 16-bit — — √ √ √ √ √ 32-bit MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-7...
Page 448: Register Descriptions
It also includes a memory attribute and selects the machine for memory operation handling. Figure 15-5 shows the BRx register. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-8 Freescale Semiconductor...
Page 449 The reset value of PS depends on the boot port size (BPS) field of the hard reset configuration word. The reset value of V depends on the boot disable (BDIS) field of the hard reset configuration word. Figure 15-6. BR0 Reset Defaults MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-9...
Page 450 0 This bank is invalid. An attempt to access this region can cause a bus monitor timeout. 1 This bank is valid. The CS signal does not assert until V is set. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-10 Freescale Semiconductor...
Page 451 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x104 (OR0) Field AM CSNT/ ACS/G5LA, SETA TRLX EHTR — G5LS Reset 1111 Addr (IMMR & 0xFFFF0000) + 0x106 Figure 15-8. OR0 Reset Defaults MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-11...
Page 452 0 Internal or external transfer acknowledge can acknowledge this access, whichever comes first. 1 The memory controller does not generate TA for this bank; instead the peripheral must generate it on the external TA signal. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-12 Freescale Semiconductor...
Page 453 Reserved, should be cleared WPER Write-protection error. Set when a write-protect error occurs on a write cycle to a write-protected bank defined by BR x [WP]. 9–15 — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-13...
Page 454 The AM x field of the RAM array entry enables address multiplexing in subsequent clock cycles. (see Table 15-19). — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-14 Freescale Semiconductor...
Page 455 CPU perform special memory operations in addition to standard read/write and periodic timer service operations. An example of this is software execution of a special UPM pattern to initialize SDRAM. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-15...
Page 456 Note that 0000 = the loop executes 16 times.) 24–25 — Reserved, should be cleared. 26–31 Memory array index. Specifies an index to one of 64 RAM words in the RAM array. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-16 Freescale Semiconductor...
Page 457 The memory address register contains an address to be driven on the external bus in the case of a command issued to the MCR. Field Reset xxxx_xxxx_xxxx_xxxx Addr (IMMR & 0xFFFF0000) + 0x164 Field Reset xxxx_xxxx_xxxx_xxxx Addr (IMMR & 0xFFFF0000) + 0x166 Figure 15-13. Memory Address Register (MAR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-17...
Page 458 The GPCM provides a CS signal for memory bank activation, WE signals for write cycles for each byte written to memory, and OE signals for read cycles. Figure 15-15 shows a simple connection between an SRAM device and the MPC885. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-18 Freescale Semiconductor...
Page 459 Asserted Asserted Asserted Asserted Data Invalid Data Invalid Read 3/4*Clk 1/4* Clk 2+SCY 1/4*Clk 1/2*Clk Write 1/4*Clk 1/4*Clk 3/4*Clk -1/4*Clk 1/2*Clk 1/2*Clk 1/4*Clk 1/2*Clk 1/2*Clk 1/4*Clk 3/8*Clk 1/4*Clk 3/8*Clk 1/2*Clk MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-19...
Page 460 MPC885 and an external peripheral device. Here, CS (the strobe output for the memory access) is connected directly to CE of the memory device and R/W is connected to the respective R/W in the peripheral device. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-20 Freescale Semiconductor...
Page 461 CE of the memory device. The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-21...
Page 462 = 1, WE and CS are negated one quarter of a clock earlier, as shown in Figure 15-20. Clock Address CSNT = 1 Data Figure 15-19. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-22 Freescale Semiconductor...
Page 463 Figure 15-21 Figure 15-22. Clock Address ACS = 10 ACS = 11 Data Figure 15-21. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-23...
Page 464 TRLX = 1), the memory controller does not support external devices that provide TA to complete the transfer with zero wait states. The minimum access duration in this case is 3 clock cycles. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-24 Freescale Semiconductor...
Page 465 Figure 15-23. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) Clock Address Data Figure 15-24. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-25...
Page 466 See Figure 15-25 through Figure 15-28 for details. Clock Address Data Hold Time Figure 15-25. GPCM Read Followed by Write (EHTR = 0) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-26 Freescale Semiconductor...
Page 467 Memory Controller Clock Address Data Hold Time Long hold time allowed Figure 15-26. GPCM Read Followed by Write (EHTR = 1) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-27...
Page 468 Memory Controller Clock Address Data Hold Time Long hold time allowed Figure 15-27. GPCM Read Followed by Read from Different Banks (EHTR = 1) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-28 Freescale Semiconductor...
Page 469 BR0. After the first write to OR0, the boot chip-select can only be restarted on hardware reset. The initial values of the boot bank in the memory controller are described in Table 15-12. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-29...
Page 470 TRLX = 0 when an external asynchronous master accesses SRAM. TA, WE, and OE remain asserted until the external master negates AS, at which point they deassert asynchronously. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-30 Freescale Semiconductor...
Page 471 During a burst cycle, the user sees the chip-select assertion follow the same pattern as for a single-beat cycle. However, BI remains negated, and the burst continues for the following data beats after the negation of chip-select following TA for the first data beat. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-31...
Page 472 RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM word with WAEN set, the external UPWAIT signal is sampled and synchronized by the memory controller and the current request is frozen (if and while UPWAIT remains asserted). MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-32 Freescale Semiconductor...
Page 473 A single-beat cycle starts with one transfer start and ends with one transfer acknowledge. For 32-bit accesses, the burst cycle starts with one transfer start but ends after four transfer acknowledges. A 16-bit bus requires 8 transfer acknowledges; an 8-bit bus requires 16. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-33...
Page 474 Program the UPMs in the following steps: 1. Write patterns into the RAM array. 2. Program MPTPR. 3. Program the machine mode register (MAMR and MBMR). 4. Set up BRx and ORx. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-34 Freescale Semiconductor...
Page 475 TSIZn. The GPL lines toggle as programmed for any access that initiates a particular pattern, but resolution of control is slightly more limited. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-35...
Page 476 G1T3 G1T4 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G1T4 G2T3 Clock Phase RAM Word RAM Word Figure 15-36. UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-36 Freescale Semiconductor...
Page 477 GCLK2_50 Signals Timing Generator CS Signal BS Signal Selected Bank TSIZ, PS, A[30:31] Selector Selector CS[0–7] GPL0 GPL1 GPL2 GPL3 GPL4 GPL5 BS[0:3] Figure 15-38. RAM Array and Signal Generation MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-37...
Page 478 1 Negated at the falling edge of GCLK2_50. CST1 Chip-select timing 1. Defines the state of CS during clock phase 2. 0 Asserted at the rising edge of GCLK1_50. 1 Negated at the rising edge of GCLK1_50. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-38 Freescale Semiconductor...
Page 479 G2T3 General-purpose line 2 timing 3. Defines the state of GPL2 during phase 4. 0 Asserted at the falling edge of GCLK1_50. 1 Negated at the falling edge of GCLK1_50. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-39...
Page 480 1 The current RAM word allows a branch to the exception pattern after the current cycle if an exception condition is detected. The exception condition can be an external device asserting TEA, HRESET, or SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-40 Freescale Semiconductor...
Page 481 CSx signal. The state of the selected CSx signal of the corresponding bank depends on the value of each CSTn bit. Figure 15-40 and the timing diagrams in Figure 15-36 Figure 15-37 shows how UPMs control CS signals. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-41...
Page 482 Figure 15-41 shows how UPMs control BS signals. Bank Selected A[30:31] TSIZ[0:1] MS[0–1] in BRx PS[0–1] in BRx UPMA Byte-Select Logic UPMB Figure 15-41. BS x Signal Selection MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-42 Freescale Semiconductor...
Page 483 15-42. This allows it to assert earlier (simultaneous with TS, for an internal master), which can speed up the memory interface, particularly when GPL5 is used as a control signal for external address multiplexers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-43...
Page 484 GPL_A5 is driven low at the falling edge of GCLK1_50 in the current UPM cycle. GPL_A5 is driven high at the falling edge of GCLK1_50 in the current UPM cycle. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-44 Freescale Semiconductor...
Page 485 Loops can be executed sequentially but cannot be nested. Table 15-17. M x MR Loop Field Usage Request Serviced Loop Field Read single-beat cycle RLFx Read burst cycle RLFx Write single-beat cycle WLFx MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-45...
Page 486 RAM word, as shown in Figure 15-43. The AMX field can be used to output the contents of MAR on the address signals. Figure 15-43 shows address multiplex timing. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-46 Freescale Semiconductor...
Page 487 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 is Enabled A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 — A10 A11 A12 A13 A14 A15 A16 A17 A18 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-47...
Page 488 1 Mbyte A20:A31 2 Mbyte A19:A31 4 Mbyte A18:A31 256 Kbyte A23:A31 512 Kbyte A22:A31 1 Mbyte A21:A31 2 Mbyte A20:A31 4 Mbyte A19:A31 8 Mbyte A18:A31 16 Mbyte A17:A31 MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-48 Freescale Semiconductor...
Page 489 32 Mbyte A18:A31 64 Mbyte A17:A31 16 Mbyte A20:A31 32 Mbyte A19:A31 64 Mbyte A18:A31 128 Mbyte A17:A31 256 Mbyte A16:A31 64 Mbyte A19:A31 128 Mbyte A18:A31 256 Mbyte A17:A31 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-49...
Page 490 8 Mbyte A20:A30 16 Mbyte A19:A30 32 Mbyte A18:A30 64 Mbyte A17:A30 32 Mbyte A19:A30 64 Mbyte A18:A30 128 Mbyte A17:A30 256 Mbyte A16:A30 128 Mbyte A18:A30 256 Mbyte A17:A30 MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-50 Freescale Semiconductor...
Page 491 GCLK2_50 instead of the rising edge, which is normal. This feature lets the user speed up the memory interface by latching data 1/2 clock early, which can be useful during burst reads. This feature should be used only in systems without external synchronous bus devices. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-51...
Page 492 If the WAEN bit is set and UPWAIT was sampled high on the previous falling edge of GCLK2_50, the logical value of the external signals are frozen to the value defined at the next falling MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-52 Freescale Semiconductor...
Page 493 LAST bit is set in a RAM word. The TODT bit is relevant only in words read by the UPM after AS is negated. For a comprehensive discussion of external bus interfacing, see Section 15.8, “External Master Support.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-53...
Page 494 The memory controller synchronized this signal because the wait signal is asynchronous. As a result of the wait signal being asserted, the UPM enters a freeze mode MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-54 Freescale Semiconductor...
Page 495 TSIZ must have a proper setup time before AS is asserted. To support asynchronous mode, SIUMCR[AEME] must be set. The memory controller synchronizes AS assertion to its internal clock and MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-55...
Page 496 If external masters exist in the system with the MPC885, address multiplexing (for DRAM for example) must be implemented in external logic. To control this external multiplexer, special features have been added to GPL5. See Section 15.6.4.4, “General-Purpose Signals (GxTx, G0x).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-56 Freescale Semiconductor...
Page 497 Asynchronous external masters behave as described in Section 15.5.3, “External Asynchronous Master Support.” CLKOUT A[0:27] A[28:31] BURST TSIZ Data Address Memory Match and Device Compare Access Figure 15-47. Synchronous External Master Access MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-57...
Page 498 ORx[G5LS]. In this example, the accessed critical word is addressed at BADDR[28:29] = 10, which then increments and wraps around to the word before the critical word (01) for subsequent beats of this burst access. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-58 Freescale Semiconductor...
Page 499 Memory Controller DRAM BS[0:3] Bank GPL_A5 Multiplexer BADDR[28:30] A[0:31] D[0:31] BURST MPC885 External Master TSIZ[0:1] Figure 15-49. Synchronous External Master Interconnect Example MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-59...
Page 500 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 15-50. Synchronous External Master: Burst Read Access to Page Mode DRAM MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-60 Freescale Semiconductor...
Page 501 ORx[G5LS]. DRAM BS[0:3] GPL_A5 Multiplexer A[:31] D[0:31] External Master TSIZ[0:1] MPC885 Arbitration Signals External Arbiter Figure 15-51. Asynchronous External Master Interconnect Example MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-61...
Page 502 Bit 24 exen Bit25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 WAIT WAIT RSS+2 Figure 15-52. Asynchronous External Master Timing Example MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-62 Freescale Semiconductor...
Page 503 The timing diagrams in Figure through Figure 15-62 can be used as a reference. Alternately, use the UPM860 or MCU unit applications for this. These applications are available at http:/www.mot.com. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-63...
Page 504 GPLA4DIS Disables the UPWAITA signal RLFA 0011 Selects three loop iterations for read WLFA 0011 Selects three loop iterations for write Selects column address on first cycle Supports burst accesses MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-64 Freescale Semiconductor...
Page 505 Bit 24 exen Bit25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 Figure 15-54. Single-Beat Read Access to Page-Mode DRAM MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-65...
Page 506 Bit 24 exen Bit25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 Figure 15-55. Single-Beat Write Access to Page Mode DRAM MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-66 Freescale Semiconductor...
Page 507 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 15-56. Burst Read Access to Page-Mode DRAM (No LOOP) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-67...
Page 508 Bit25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 15-57. Burst Read Access to Page-Mode DRAM (LOOP) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-68 Freescale Semiconductor...
Page 509 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 Figure 15-58. Burst Write Access to Page-Mode DRAM (No LOOP) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-69...
Page 510 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 Figure 15-59. Burst Write Access to Page-Mode DRAM (LOOP) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-70 Freescale Semiconductor...
Page 511 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 15-60. Refresh Cycle (CAS before RAS) to Page-Mode DRAM MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-71...
Page 512 For a 16-bit port size memory, the reduction is from 17 to 10 cycles and when an 8-bit port size memory is connected, the reduction is from 33 to 18 cycles. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-72 Freescale Semiconductor...
Page 513 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 Figure 15-62. Optimized DRAM Burst Read Access MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-73...
Page 514 — Program the RAM array using MCR and MDR. The RAM word must be written into the MDR before a command is issued to the MCR. Repeat this step for all RAM word entries. WRITE — Initialize ORx and BRx for the required DRAM device address mapping. MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-74 Freescale Semiconductor...
Page 515 GPLB4DIS Disables the UPWAITB signal RLFB 0011 Selects three loop iterations for read WLFB 0011 Selects three loop iterations for write Selects column address on first cycle Supports burst accesses MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-75...
Page 516 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 15-64. EDO DRAM Single-Beat Read Access MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-76 Freescale Semiconductor...
Page 517 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+2 WSS+3 Figure 15-65. EDO DRAM Single-Beat Write Access MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-77...
Page 518 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+10 Figure 15-66. EDO DRAM Burst Read Access MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-78 Freescale Semiconductor...
Page 519 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9 Figure 15-67. EDO DRAM Burst Write Access MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-79...
Page 520 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 15-68. EDO DRAM Refresh Cycle (CAS before RAS) MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-80 Freescale Semiconductor...
Page 521 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 15-69. EDO DRAM Exception Cycle MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 15-81...
Page 522 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 xxS+1 xxS+2 xxS+3 xxS+4 xxS+5 xxS+6 xxS+7 xxS+8 xxS+9 xxS+10 Figure 15-70. Blank Work Sheet for a UPM MPC885 PowerQUICC Family Reference Manual, Rev. 2 15-82 Freescale Semiconductor...
Page 523 PCMCIA signals shared among all sockets consist of the address and data buses, socket control signals, and synchronous socket status signals. A[6:31] and D[0:15] are the address and data signals of the system bus. Figure 16-1 shows the PCMCIA host adapter module’s external signals. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-1...
Page 524 V CC _A ALE_A/B Latch with OE WAIT_A/B, IOIS16_A/B RDY/BSY_x, BVD1_x, BVD2_x Chip V DD CD1_x, CD2_x, VS1_x, VS2_x Transparent latch SPKROUT for voltage conversion Figure 16-1. System with Two PCMCIA Sockets MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-2 Freescale Semiconductor...
Page 525 Write enable/program. Output. During PCMCIA accesses, WE_x is used to latch memory write data to the PC card in a PCMCIA socket. Can also be used as the programming strobe for PC cards using programmable memory technologies. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-3...
Page 526 “signal on change” bit and “changed” bit in the card status register on the PC card are either or both zero. STSCHG_x must be asserted when both bits = 1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-4 Freescale Semiconductor...
Page 527 Note: General purpose timer 1 can be used to drive SPKROUT. When enabled, timer 1 is exclusive ORed with the resulting exclusive OR of the SPKR_A and SPKR_B input signals to generate SPKROUT. See Section 17.2.2.6, “Timer 1 and SPKROUT.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-5...
Page 528 20 ns (50 MHz) 30 ns (33.3 MHz) 40 ns (25 MHz) 62 ns (16 MHz) 83 ns (12 MHz) Setup time worst-case is for a write. In these cases, setup=data_set_up_before_iord +1 clock. MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-6 Freescale Semiconductor...
Page 529 PGCRx[CxDREQ]. If the internal DMA request is disabled, the DMA request is assumed to be DREQ0/DREQ1 and port C should assign PC15/14 as DREQ0/DREQ1. If the request is enabled, port C should not be programmed to be DREQ0/DREQ1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-7...
Page 530 Status of inputs from the PCMCIA card to the host (BVD, CD, RDY, VS) is reported to the PIPR, shown Figure 16-3. PIPR is a read-only register; write operations are ignored MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-8 Freescale Semiconductor...
Page 531 Card detect 1 for card B CBBVD2 Battery voltage/SPKR_B input for card B CBBVD1 Battery voltage/STSCHG_B input for card B CBRDY RDY/IRQ of card B pin 24–31 — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-9...
Page 532 RDY/IRQ of card A pin falling edge detected. Device and socket interrupt. 12–15 — Reserved, should be cleared. CBVS1_C Voltage sense 1 for card B changed CBVS2_C Voltage sense 2 for card B changed MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-10 Freescale Semiconductor...
Page 533 Addr (IMMR & 0xFFFF0000) + 0x0F8 28-31 — CB ERDY ERDY ERDY ERDY — Field Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x0FA Figure 16-5. PCMCIA Interface Enable Register (PER) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-11...
Page 534 Reserved, should be 0. CB_ERDY_L Enable for RDY/IRQ of card B pin is low CB_ERDY_H Enable for RDY/IRQ card B pin is high CB_ERDY_R Enable for RDY/IRQ card B pin rising edge detected MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-12 Freescale Semiconductor...
Page 535 CxRESET Card x reset. CARESET is reflected on OP0 used to reset card A. CBRESET is reflected on OP3 used to reset card B. 26–31 — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-13...
Page 536 Reset Undefined Addr (IMMR & 0xFFFF0000) + 0x086 (POR0); 0x08E (POR1); 0x096 (POR2); 0x09E (POR3); 0x0A6 (POR4); 0x0AE (POR5); 0x0B6 (POR6); 0x0BE (POR7) Figure 16-8. PCMCIA Option Register 0–7 (POR0–POR7) MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-14 Freescale Semiconductor...
Page 537 1111 1100 0000 0000 0000 0000 0000 0000 Addr & MASK = PBA & MASK for a valid PCMCIA access; otherwise, it is not a valid PCMCIA access 5–11 — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-15...
Page 538 1 Write protected. Attempting to write to this window causes a machine check interrupt. PCMCIA valid. Indicates whether the contents of the OBR and POR pair are valid. 0 This bank is invalid. 1 This bank is valid. MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-16 Freescale Semiconductor...
Page 539 PCMCIA controller timings. CLKOUT A[6:31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSST PSHT Figure 16-9. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-17...
Page 540 PCMCIA Interface CLKOUT A[6:31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSST PSHT Figure 16-10. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-18 Freescale Semiconductor...
Page 541 PCMCIA Interface CLKOUT A[6:31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSHT PSST Figure 16-11. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-19...
Page 542 PCMCIA Interface CLKOUT A[6:31] RD/WR BURST CE1/CE2 PCWE WAIT Data PSST PSHT Figure 16-12. PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-20 Freescale Semiconductor...
Page 543 PCMCIA Interface CLKOUT A[6:31] RD/WR BURST CE1/CE2 IOWR WAIT Data IO16 PSST PSHT Figure 16-13. PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-21...
Page 544 A[6:31] RD/WR BURST CE1/CE2 IOWR WAIT Data PSHT PSST Wait Delay Figure 16-14. PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 0 MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-22 Freescale Semiconductor...
Page 545 A[6:31] RD/WR BURST CE1/CE2 IORD WAIT Data PSST Wait Delay PSHT Figure 16-15. PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-23...
Page 546 PCMCIA Interface CLKOUT A[6:31] RD/WR BURST IOWR Data IO16 PSHT PSST Figure 16-16. PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-24 Freescale Semiconductor...
Page 547 A[6:31] RD/WR BURST IOWR Data IO16 PSHT PSHT PSST PSST Figure 16-17. PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 16-25...
Page 548 SIZE SIZE = Word SIZE = Half Data PSHT PSHT PSST PSST Figure 16-18. PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0 MPC885 PowerQUICC Family Reference Manual, Rev. 2 16-26 Freescale Semiconductor...
Page 549 IrDA use of HDLC framing techniques with UART-type characters. • Chapter 26, “SCC BISYNC Mode,” describes the MPC885 implementation of byte-oriented BISYNC protocol developed by IBM for use in networking products. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 550 This document uses the following notational conventions: Bold entries in figures and tables showing registers and parameter RAM should Bold be initialized by the user. mnemonics Instruction mnemonics are shown in lowercase bold. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 551 Condition/indication channel used in the GCI protocol Communications processor Communications processor module Direct memory access DPLL Digital phase-locked loop DRAM Dynamic random access memory DSISR Register used for determining the source of a DSI exception MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 552 Nonmultiplexed serial interface Open systems interconnection Peripheral component interconnect Pulse-position modulation RTOS Real-time operating system Receive Serial communications controller Serial control port SDLC Synchronous Data Link Control SDMA Serial DMA Serial interface MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 553 Serial peripheral interface SRAM Static random access memory Time-division multiplexed Terminal endpoint of an ISDN connection Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 554 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 555 The MPC885 CPM is similar to the one in the MPC860 and both are derived from the CPM in the MC68360 QUICC; see the MC68360 Quad Integrated Communications Controller (QUICC) User’s Manual. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 17-1...
Page 556 — Two independent DMA channels for memory-to-memory transfers or interfacing external peripherals — RISC timer tables • Three full-duplex serial communications controllers (SCCs) that support the following: — UART protocol (asynchronous or synchronous) — HDLC protocol — AppleTalk protocol MPC885 PowerQUICC Family Reference Manual, Rev. 2 17-2 Freescale Semiconductor...
Page 557 SCCs and SMCs onto two time-division multiplexed (TDM) interfaces • Four independent baud rate generators (BRGs) • Four general-purpose 16-bit timers or two 32-bit timers • CPM interrupt controller (CPIC) • General-purpose I/O ports MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 17-3...
Page 558 • Timer mode register (TMR) • Timer capture register (TCR) • Timer counter (TCN) • Timer reference register (TRR) • Timer event register (TER) • Timer global configuration register (TGCR). MPC885 PowerQUICC Family Reference Manual, Rev. 2 17-4 Freescale Semiconductor...
Page 559 The following subsections describe the timer operation. The timer mode registers (TMRx) and the timer global configuration register (TGCR) mentioned in this section are described in Section 17.2.3, “CPM Timer Register Set.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 17-5...
Page 560 Pulse measurement—The restart gate mode can measure a low pulse on TGATEx. The rising edge of TGATEx completes the measurement. If TGATEx is externally connected to TINx, it causes the timer to capture the count value and generate a rising-edge interrupt. MPC885 PowerQUICC Family Reference Manual, Rev. 2 17-6 Freescale Semiconductor...
Page 561 To prevent timer 1 from affecting SPKROUT, either use the timer in a pulse mode or do not enable it. 17.2.3 CPM Timer Register Set The following subsections discuss the CPM timer register set. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 17-7...
Page 562 0 Restart gate mode. A falling TGATE1 enables and restarts the count and a rising edge of TGATE1 disables the count. 1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart the count value in the TCN. MPC885 PowerQUICC Family Reference Manual, Rev. 2 17-8 Freescale Semiconductor...
Page 563 11 Corresponding TIN x signal (falling edge) Gate enable. 0 TGATE x is ignored. 1 TGATE x is used to control the timer—TGATE1 for timer 1 and 2, TGATE2 for timer 3 and 4. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 17-9...
Page 564 Note that the counter registers may not be updated correctly if a write is made while the timer is not running. Use TRRx to define the preferred count value.These registers are affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 17-10 Freescale Semiconductor...
Page 565 5. Write TER2 = 0xFFFF to clear TER2 of any previous events. 6. Set CIMR = 0x0004_0000 to enable timer 2 interrupts in the CPIC and initialize the CICR. 7. Set TGCR = 0x0010 to enable timer 2 to begin counting. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 17-11...
Page 566 7. Set CIMR = 0x0004_0000 to enable timer 2 interrupts in the CPIC and initialize the CICR. 8. Set TGCR = 0x0091 to enable timers 1 and 2 to begin counting in cascaded mode. MPC885 PowerQUICC Family Reference Manual, Rev. 2 17-12 Freescale Semiconductor...
Page 567 Supports general-purpose DMA using two IDMA channels • Supports DMA bursting for memory-to-memory IDMA • Performs DMA of serial data to external memory • RISC timer table supports a maximum of 16 software timers MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-1...
Page 568 SCC2–SCC4 receive and transmit FIFOs are 16 bytes each. The serial management controllers (SMCs), serial peripheral interface (SPI), and I C are all double-buffered, creating effective FIFO sizes of two characters.The parallel interface port (PIP) is a single register interface. MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-2 Freescale Semiconductor...
Page 569 SPI Tx C Rx C Tx RISC timer table IDMA emulation: DREQ0 (option 3) IDMA emulation: DREQ1 (option 3) See the RCCR[DRQP] description in Section 18.6.1, “RISC Controller Configuration Register (RCCR).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-3...
Page 570 In the future, this register may be used for additional purposes. Figure 18-2 shows the CPMCFG register. Field — Reset — Addr DPRAMbase + 0x1CB8 Field AAL2 — Reset — Addr DPRAMbase + 0x1CBA Figure 18-2. CPM Configuration Register (CPMCFG) MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-4 Freescale Semiconductor...
Page 571 Timer enable. Controls whether the CP’s internal timer sends a tick to the CP based on the value programmed in the timer period (TIMEP). 0 Stop RISC timer table scanning 1 Start RISC timer table scanning — Reserved. Should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-5...
Page 572 RAM can contain executable microcode. RMDS is used with RCCR[ERAM] to determine the valid address space for executable microcode. Section 18.7.1, “System RAM and Microcode Packages,” describes the partitioning of the dual-port system RAM. MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-6 Freescale Semiconductor...
Page 573 FLG. Note that the CPCR has a different bit format for ATM operations; see Section 39.4, “Port-to-Port (PTP) Switching.” Field RST — OPCODE CH_NUM — Reset Addr 0x9C0 Figure 18-5. CP Command Register (CPCR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-7...
Page 574 INIT RX PARAMS INIT RX INIT RX PARAMS PARAMS PARAMS PARAMS 0010 — — — INIT TX INIT TX INIT TX PARAMS INIT TX INIT TX PARAMS PARAMS PARAMS PARAMS MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-8 Freescale Semiconductor...
Page 575 Graceful stop transmission. Stops the transmitting channel after the whole current frame has been GRACEFUL sent. Transmission continues when is issued and the ready bit is set in the next TxBD. STOP TX RESTART TX MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-9...
Page 576 The entire dual-port RAM should be cleared as the first step in system initialization. This step should be followed by issuing a CPM reset using the CPCR. Only after these two steps should the dual-port RAM be programmed for specific CPM functions. MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-10 Freescale Semiconductor...
Page 577 The controller and sub-block parameters of the parameter RAM and the optional microcode packages in system RAM use fixed addresses. The buffer descriptors, buffers, and scratch pad area, however, can be located in any unused dual-port RAM area. See Figure 18-7. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-11...
Page 578 18-7. In addition to RCCR[ERAM], RMDS[ERAM4K] (enable RAM microcode at offset 4K) affects the system RAM memory configuration for microcode packages. Setting RMDS[ERAM4K] locks a 2-Kbyte block and a 512-byte extension (the lighter-shaded areas of Figure 18-7) for microcode execution. MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-12 Freescale Semiconductor...
Page 579 Miscellaneous 0x1CC0—0x1CFF IDMA1 0x3D00 0x1D00—0x1D7F SCC2 0x1D80—0x1DAF SPI default area 0x1DB0—0x1DBF RISC timer table 0x1DC0—0x1DFF IDMA2 0x3E00 0x1E00—0x1E7F SCC3 0x1E80—0x1EBF SMC1 0x1EC0—0x1EFF Reserved 0x3F00 0x1F00—0x1F7F SCC4 0x1F80—0x1FBF SMC2/PIP 0x1FC0—0x1FFF Reserved MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-13...
Page 580 “Using the RISC Timers to Track CP Loading.” The timer table is configured using the RCCR, the timer table parameter RAM, and the RISC controller timer event/mask registers (RTER/RTMR), and by issuing to the CPCR. SET TIMER MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-14 Freescale Semiconductor...
Page 581 18-8. 16 RISC Timer Table Entries (Up to 64 Bytes) Timer Table Base Pointer DPRAM_BASE + 0x1DB0 TM_BASE RISC Timer Table Parameter RAM Figure 18-8. RISC Timer Table RAM Usage MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-15...
Page 582 Valid. When set, this bit enables the timer. It should be cleared to disable the timer. Restart. Should be set for an automatic restart or cleared for a one-shot timer operation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-16 Freescale Semiconductor...
Page 583 The RISC timer table bit in the CPM interrupt mask register, CIMR[RTT], described in Section 35.5.3, “CPM Interrupt Mask Register,” acts as a global RISC timer interrupt mask. Clearing CIMR[RTT] masks all RISC timer interrupts, regardless of RTMR. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-17...
Page 584: Pwm Mode
5. Configure the RTMR to enable the timers that need to generate interrupts. A one enables interrupts. 6. Set CIMR[RTT] to generate interrupts to the system. The CPIC may require initialization not mentioned here; see Chapter 35, “CPM Interrupt Controller.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-18 Freescale Semiconductor...
Page 585 CP performance to its limit. Incorporate the following steps to the standard initialization sequence: 1. Program RCCR[TIMEP] to 0b001111 for a table scan tick of 16 × (1,024) = 16,384. 2. Disable RISC timer table interrupts, if preferred. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 18-19...
Page 586 15. If the difference between them exceeds two ticks, the CP has, during some scan tick interval, exceeded the 96% utilization level. Note that when comparing timer counts, the general-purpose timers are up-counters, while RISC timers are down-counters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 18-20 Freescale Semiconductor...
Page 587 SIU is configured in show-cycles mode. Thus, in normal operation, U-bus transfers occur simultaneously with external system bus operations. The description is the same for the FECs and the security engine. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-1...
Page 588 If an SDMA bus error occurs, all CPM activity ceases and the entire CPM must be reset in the CPM command register (CPCR); see Section 18.6.3, “CP Command Register (CPCR).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-2 Freescale Semiconductor...
Page 589 16-bit memory takes two consecutive bus cycles. An SDMA steals cycles with no arbitration overhead unless an external device is bus master. Figure 19-2 shows an SDMA stealing a cycle from an internal bus master. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-3...
Page 590 HRESET but is not affected by SRESET. Figure 19-3 shows the register format. Field — Reset 0000_0000_0000_0000 Addr IMMR + 0x030 Field — Reset 0000_0000_0000_0000 Addr IMMR + 0x032 Figure 19-3. SDMA Configuration Register (SDCR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-4 Freescale Semiconductor...
Page 591 SDMR is set, the corresponding interrupt in the SDSR is enabled; if the bit is cleared, the corresponding interrupt is masked. Reset clears SDMR. Its internal address (IMMR offset) is 0x90C. This register is affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-5...
Page 592 Support for all bus-termination modes, such as TA, TEA, and BI • DMA handshaking for cycle-steal and burst transfers • Two buffer handling modes—auto-buffering and buffer-chaining • The MPC885’s chip-select and wait-state generation logic can be used with IDMA. MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-6 Freescale Semiconductor...
Page 593 IDMA2 base = IMMR + 0x3DC0 19.3.3 IDMA Registers Each IDMA channel has a DMA channel mode register (DCMR), an IDMA status register (IDSR) and corresponding mask register (IDMR) that contain global channel parameters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-7...
Page 594 Note that for memory/memory accesses, the CP automatically increments the address and does not use SDACK n . Single-cycle. Selects single- or dual-cycle mode 0 Dual-cycle (dual-address) mode 1 Single-cycle (single-address) mode MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-8 Freescale Semiconductor...
Page 595 The BDs are grouped together in contiguous dual-port RAM to form a standard BD table; see Figure 19-7. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-9...
Page 596 The word at (offset + 0xC) points to the beginning of the destination buffer in internal or external memory. — When the destination is a peripheral, this field is ignored in single-address mode. In dual-address mode, this field contains the peripheral address. MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-10 Freescale Semiconductor...
Page 597 0 Normal mode (buffer-chaining). The CP clears the V bit after this descriptor is processed. 1 Continuous mode (auto-buffering). The CP does not clear the V bit after this descriptor is processed. 7–15 — Reserved MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-11...
Page 598 Set the L bit (last) in the status-and-control field to mark the last BD of a chain. When the CPM completes a chain, it flags IDSR[DONE], triggering a maskable interrupt to the core. The I bit (individual BD MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-12 Freescale Semiconductor...
Page 599 IDMA internal registers to determine the status of the channel or to alter parameters. If PCSO[DREQ] is set again while a transfer request is pending, the channel arbitrates for the bus and continues normal operation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-13...
Page 600 Since DREQ0 and DREQ1 are multiplexed through PC15 and PC14 respectively, the port C pin assignment register and direction register must be configured as well; see Section 34.4, “Port C.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-14 Freescale Semiconductor...
Page 601 Dual-address source read—SAPR drives the address bus, SFCR drives the address type, and DCMR drives the size control. Data is read from the memory or peripheral and placed in internal MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-15...
Page 602 Figure 19-10 Figure 19-11 show the transaction timing diagrams for asynchronous and synchronous single-address peripheral writes. See Section 19.3.7, “IDMA Interface Signals—DREQ and SDACK,” for more on IDMA handshake signals. MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-16 Freescale Semiconductor...
Page 603 Figure 19-10. SDACK Timing Diagram: Single-Address Peripheral Write, Externally Generated TA CLKOUT Address SETUP HOLD Data SDACK DELAY PHOLD Figure 19-11. SDACK Timing Diagram: Single-Address Peripheral Write, Internally Generated TA MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-17...
Page 604 Reset—On an external reset, an IDMA immediately aborts channel operation, returns to the idle state, and clears the IDSR. If a bus cycle is in progress, the cycle is terminated, the control and MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-18 Freescale Semiconductor...
Page 605 TEA to detect a bus exception for the current bus cycle. TEA terminates the cycle immediately and negates SDACK, which is used to control the transfer to or from the device. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 19-19...
Page 606 SDMA Channels and IDMA Emulation MPC885 PowerQUICC Family Reference Manual, Rev. 2 19-20 Freescale Semiconductor...
Page 607 If the TSA is not required for routing data to and from the SCCs and SMCs, it can still be used to generate complex waveforms on its four strobe output pins (L1ST[1–4]). For example, the user can program the TSA to implement stepper motor control signals of variable duty cycle and period. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-1...
Page 608 QUICC Multichannel Controller (QMC) see the Supplement, QUICC™ Multichannel Controller — Up to 64 independent communication channels — Arbitrary mapping of any of 0–63 channels to any of 0–63 TDM time slots MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-2 Freescale Semiconductor...
Page 609 Bit or byte resolution in routing, masking, and strobe selection • Supports frames up to 8,192 bits long • Internal routing and strobe selection can be programmed dynamically. • Supports automatic echo and loopback modes for each TDM channel MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-3...
Page 610 For more flexibility, the user can also provide separate Rx and Tx syncs as well as independent clocks. Figure 20-2 shows example TSA configurations ranging from the simplest to the most complex. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-4 Freescale Semiconductor...
Page 611 MPC885 TDM Tx Sync TDM Tx Clk SCC2 SMC1 SCC2 TDM Tx TDM Rx Sync TDM Rx Clk TDM Rx SCC2 SMC1 Figure 20-2. Various Configurations of a TDM Channel MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-5...
Page 612 64 entries are for programming receive routing, and the second 64 are for transmit routing. The entries define the number of bits or bytes to be routed to and from the SCCs or SMCs and also control external strobes. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-6 Freescale Semiconductor...
Page 613 IDL request (output) and grant (input) signals. Used if D-channel arbitration is required. Note that if the receive and transmit clocks and the synchronization signals are common, L1TSYNCx and L1TCLKx are not needed. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-7...
Page 614 Two TDM channels with static routing—Rx and Tx RAMs are halved. • A single TDM channel with dynamic routing—Rx and Tx RAMs are halved. • Two TDM channels with dynamic routing—Rx and Tx RAMs are quartered. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-8 Freescale Semiconductor...
Page 615 In a configuration with two multiplexed channels with static frames, shown in Figure 20-6, there are 32 entries for Tx data/strobe routing and 32 entries for Rx data/strobe routing for each TDM channel. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-9...
Page 616 • 128–191 Rxb route • 256–319 Txa route • 384–447 Txb route The shadow RAMs are at addresses: • 64–127 Rxa route • 192–255 Rxb route • 320–383 Txa route MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-10 Freescale Semiconductor...
Page 617 The entire SI RAM is always readable, but only the shadow RAM is safe to write. The SI status register (SISTR) can be read to determine which part of the RAM is the current-route RAM. The SI RAM pointer MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-11...
Page 618 L1RCLKb L1RSYNCa L1RSYNCb Route Route Shadow Shadow 16 Entries 16 Entries L1TCLKa L1TCLKb L1TSYNCa L1TSYNCb Route Route Shadow Shadow Figure 20-9. SI RAM Partitioning Using Two TDMs with Dynamic Frames MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-12 Freescale Semiconductor...
Page 619 SI RAM for TDMb, for example), the assertion of the strobe corresponds to the logical OR of all possible sources. It is recommended that a given strobe be used in only one set of SI RAM entries. — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-13...
Page 620 L1TXD while sending on L1RXD, clear the CSEL bits in corresponding Rx SI RAM entries. Note that using the SWTR option may cause data collisions with other stations unless an empty (quiet) time slot is used. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-14 Freescale Semiconductor...
Page 621 The following sections describe the SI registers. 20.2.4.1 SI Global Mode Register (SIGMR) The SI global mode register (SIGMR), shown in Figure 20-12, defines the SI RAM division modes and enables the individual TDM channels. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-15...
Page 622 TDM transmit pin with the first frame because the SCCs require start-up clocking at initialization. Expect a number of bytes of idle (typically 10–15) depending on the size of the frame and number of time slots routed to the particular SCC. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-16 Freescale Semiconductor...
Page 623 L1RXD x . Transmitter output L1TXD x and L1RQ x are inactive. Provides loopback testing of the entire TDM without affecting the external serial lines. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-17...
Page 624 Frame sync edge for TDMa/b. Indicates when L1RSYNC x and L1TSYNC x pulses are sampled with the falling/rising edge of the channel clock. 0 Falling edge. Use for IDL and GCI 1 Rising edge MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-18 Freescale Semiconductor...
Page 625 Bit-1 Bit-2 Bit-3 Bit-4 Bit-0 Bit-1 Bit-2 No Delay from Sync Latch to First Bit of Frame Figure 20-15. No Delay from Sync to Data ( x FSD = 00) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-19...
Page 626 L1ST is Driven from Clock Low L1ST in Both the FE Settings (On Bit-0) Rx Sampled Here Figure 20-17. Falling Edge (FE) Effect When CE = 0 and x FSD = 01 MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-20 Freescale Semiconductor...
Page 627 (FE=1) L1TXD (Bit-0) L1ST and Data Bit-0 is Driven L1ST from Clock Low. (On Bit-0) Figure 20-18. Falling Edge (FE) Effect When CE = 1 and x FSD = 00 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-21...
Page 628 20-20, selects the SCC clock source from one of four baud rate generators or an input from the bank of clock pins. The SICR also connects the SCCs to the TSA and enables the grant mechanism chosen in SIMODE. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-22 Freescale Semiconductor...
Page 629 RUSB Receive/transmit clock source for the USB. 000 BRG1 29–31 TUSB 001 BRG2 010 BRG3 011 BRG4 100 CLK1 for USB 101 CLK2 for USB 110 CLK3 for USB 111 CLK4 for USB MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-23...
Page 630 CRORb CROTb — Reset Addr OxAE6 Figure 20-22. SI Status Register (SISTR) This register is affected by HRESET but is not affected by SRESET. Table 20-8 describes the SISTR fields. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-24 Freescale Semiconductor...
Page 631 One of the four strobes can be connected externally to an interrupt pin to generate an interrupt on a particular SI RAM entry to start or stop TSA execution. The pointers in SIRP indicate the SI RAM entry word offset that is in progress. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-25...
Page 632 • If VTa = 1, TaPTR points to the active Txa entry. The Tx address block is 256–383; SISTR[CROTa] = 0. • If VTb = 1, TbPTR points to the active Txa entry. The Tx address block is 384–511; SISTR[CROTa] = 1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-26 Freescale Semiconductor...
Page 633 IDL interface connects the 2B+D channels between the MPC885, CODEC, and S/T transceiver. An SCC is configured in HDLC mode to handle the D channel. Another SCC is used to rate adapt the terminal MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-27...
Page 634 L1GRx—IDL grant permission to transmit on the D channel. Input to the MPC885 on L1TSYNCx The basic rate IDL bus has three channels: • B1 is a 64-Kbps bearer channel • B2 is a 64-Kbps bearer channel • D is a 16-Kbps signaling channel MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-28 Freescale Semiconductor...
Page 635 IDL interface and the serial controller. The receiver accepts only the bits enabled by the Rx route RAM. Likewise, the transmitter sends only the bits enabled in the Tx route RAM and three-states L1TXDx. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-29...
Page 636 PCDIR. L1RSYNCa is an input but does not need to be configured in PCDIR. 9. PDPAR[6] Configure L1RQa, 10. PCDIR[6] = 0. L1RQa is an output. SIGMR = 0x04. Enable TDMa (one static TDM). 11. SICMR is not used. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-30 Freescale Semiconductor...
Page 637 L1RCLKx divided by 2. L1CLK (2X the Data Rate) L1SYNC L1RXD M (Monitor) D1D2 L1TXD M (Monitor) D1D2 Notes: Clock is not to scale. L1CLKO is not shown. Figure 20-27. GCI Bus Signals MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-31...
Page 638 For normal mode operation, first program the channels’ SIMODE[DSCx, FEx, CEx, RFSDx] for GCI/SCIT mode, defining the sync pulse to GCI sync for framing and the data clock as one-half the input MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-32 Freescale Semiconductor...
Page 639 6 bits SMC1 (I + A + E) 0000 0110 Skip 7 bytes 0000 0001 Skip 2 bits 0000 0000 D grant bit 2. SIMODE = 0x8000_80E0. Only TDMa is used. SMC1 and SMC2 are connected. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-33...
Page 640 MPC885. Note the internal RCLKx and TCLKx can be used as inputs to the DPLL unit, which is inside the SCCx; thus, RCLKx and TCLKx are not always required to reflect the actual bit rate on the line. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-34 Freescale Semiconductor...
Page 641 The SCC3 in NMSI mode has its own set of modem control signals: • TXD3 • RXD3 TCLK3 ← BRG1–BRG4, CLK5–CLK8 • RCLK3 ← BRG1–BRG4, CLK5–CLK8 • • RTS3 • CTS3 • MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-35...
Page 642 A 16x divider option allows slow baud rates at high system frequencies • Each BRG contains an autobaud support option • Each BRG output can be routed to a pin (BRGOn) MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-36 Freescale Semiconductor...
Page 643 BRG clock cycle (no spikes occur on the BRGO output clock). BRGC can be changed on the fly; however, two changes should not occur within a time equal to two source clock periods. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-37...
Page 644 Section 20.4.2, “Autobaud Operation on the SCC UART.” 0 Normal operation of the BRG 1 When RXD goes low, the BRG determines the length of the start bit and synchronizes the BRG to the actual baud rate. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-38 Freescale Semiconductor...
Page 645 BRG before the autobaud process begins. To do this, first clear BRGC[ATB] and enable the BRG receive clock to the highest frequency. Then, immediately before the autobaud process starts (after device initialization), set BRGCn[ATB]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 20-39...
Page 646 = (BRGCLK or CLK2 or CLK6) ÷ (1 or 16 according to BRGCx[DIV16]) ÷ (clock divider + 1) For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz, DIV16 = 0, and the clock divider = 389. MPC885 PowerQUICC Family Reference Manual, Rev. 2 20-40 Freescale Semiconductor...
Page 647 Although the selected protocol usually applies to both the SCC transmitter and receiver, one half of an SCC can run transparent operations while the other half runs a standard protocol (except Ethernet and serial ATM as applicable). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-1...
Page 648 (UART), AppleTalk/LocalTalk, and totally transparent protocols • Supports 10-Mbps Ethernet/IEEE 802.3 (half- or full-duplex) • Additional protocols can be added in the future through the use of RAM microcodes. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-2 Freescale Semiconductor...
Page 649 GSMR_L contains the low-order 32 bits; GSMR_H, shown in Figure 21-2, contains the high-order 32 bits. Some GSMR operations are described in later sections. These registers are affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-3...
Page 650 TTX and TRX) and sends the msb of each byte first. Section 26.11, “BISYNC Mode Register (PSMR),” describes reversing bit order in a BISYNC protocol. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-4 Freescale Semiconductor...
Page 651 CTS is asserted to the SCC. Assuming CTS is asserted, transmission begins 8 clocks after the receiver starts receiving data. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-5...
Page 652 0xA20 (GSMR_L2), 0xA40 (GSMR_L3), 0xA60 (GSMR_L4) Field RDCR RENC TENC DIAG ENR ENT MODE Reset Addr 0xA22 (GSMR_L2), 0xA42 (GSMR_L3), 0xA62 (GSMR_L4) Figure 21-3. GSMR_L—General SCC Mode Register (Low Order) MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-6 Freescale Semiconductor...
Page 653 010 16 bits (2 bytes) 011 32 bits (4 bytes) 100 48 bits (6 bytes). Select this setting for Ethernet operation. 101 64 bits (8 bytes) 110 128 bits (16 bytes) 111 Reserved MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-7...
Page 654 000 NRZ (default setting if DPLL is not used). Required for UART (synchronous or asynchronous). 001 NRZI Mark (set RINV/TINV also for NRZI space). 010 FM0 (set RINV/TINV also for FM1). 011 Reserved 100 Manchester 101 Reserved 110 Differential Manchester (Differential Bi-phase-L) 111 Reserved MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-8 Freescale Semiconductor...
Page 655 0001 Reserved 0010 AppleTalk/LocalTalk 0011 SS7—reserved for RAM microcode 0100 UART 0101 Reserved 0110 Asynchronous HDLC or IrDA 0111 Reserved. 1000 BISYNC 1001 Reserved 101x Reserved 1100 Ethernet All others reserved MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-9...
Page 656 TODR[TOD] after TxBD[R] is set. Because this feature favors the specified TxBD, it may affect servicing of the FIFOs of other CPM controllers. Therefore, transmitting on demand should only be used MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-10 Freescale Semiconductor...
Page 657 — For a TxBD, this pointer can be even or odd. Shown in Figure 21-6, the format of Tx and Rx BDs is the same in each SCC mode. Only the status and control bits differ for each protocol. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-11...
Page 658 The CP detects that the BD is ready when it polls the R bit or when the user writes to the TODR. After data from the BD is put in the Tx FIFO, if necessary the CP waits for the next MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-12 Freescale Semiconductor...
Page 659 0x04 RFCR Byte Rx function code. See Section 21.4.1, “Function Code Registers (RFCR and TFCR).” 0x05 TFCR Byte Tx function code. See Section 21.4.1, “Function Code Registers (RFCR and TFCR).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-13...
Page 660 From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4) These parameters need not be accessed for normal operation but may be helpful for debugging. For CP use only MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-14 Freescale Semiconductor...
Page 661 To allow interrupt handling for SCC-specific events, further event, mask, and status registers are provided within each SCC’s internal memory map area; see Table 21-7. Since interrupt events are protocol-dependent, event descriptions are found in the specific protocol chapters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-15...
Page 662 4. If the time-slot assigner (TSA) is used, the serial interface (SI) must be configured. If the SCC is used in NMSI mode, SICR must still be initialized. 5. Write all GSMR bits except ENT or ENR. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-16 Freescale Semiconductor...
Page 663 Last Bit of Frame Data (Output) (Input) NOTE: 1. A frame includes opening and closing flags and syncs, if present in the protocol. Figure 21-9. Output Delay from RTS Asserted for Synchronous Protocols MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-17...
Page 664 Negating CTS forces RTS high and Tx data to become idle. If GSMR_H[CTSS] is zero, the SCC must sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 21-11. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-18 Freescale Semiconductor...
Page 665 21-12. If GSMR_H[CDS] is zero, CD is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS] is 1, CD transitions cause data to be immediately gated into the receiver. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-19...
Page 666 If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0, transmission begins in three additional bit times. • If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 1, transmission begins in two additional bit times. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-20 Freescale Semiconductor...
Page 667 RCLK EDGE Carrier SNC DPLL TSNC Noise Receiver RINV Hunting 1x Mode Decoded Data HSRCLK RINV SCCR Data RENC ≠ NRZI 1x Mode HSRCLK Figure 21-13. DPLL Receiver Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-21...
Page 668 In some protocols, the preceding flags or syncs can function as a preamble; others use the patterns in Table 21-8. When transmission occurs, the SCC can generate preamble patterns, as programmed in GSMR_L[TPP, TPL]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-22 Freescale Semiconductor...
Page 669 Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential Manchester. Figure 21-15 shows the different encoding methods. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-23...
Page 670 A zero is represented by a transition at the center of the bit with the same polarity from the transition at the center of the preceding bit. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-24 Freescale Semiconductor...
Page 671 3, issue a INIT TX PARAMETERS RESTART TRANSMIT command. 5. Set GSMR_L[ENT]. Transmission begins using the TxBD pointed to by TBPTR, assuming the R bit is set. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 21-25...
Page 672 3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol. 21.4.8 Saving Power To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 21-26 Freescale Semiconductor...
Page 673 In multidrop mode, frames of characters are broadcast with the first character acting as a destination address. To accommodate this, the UART frame is extended one bit to distinguish address characters from normal data characters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-1...
Page 674 UART mode register (PSMR) define the length and format of the UART character. Bits are received in the following order: 1. Start bit 2. 5–8 data bits (lsb first) MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-2 Freescale Semiconductor...
Page 675: Synchronous Mode
22.4 SCC UART Parameter RAM For UART mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 22-1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-3...
Page 676 XOFF and XON, into the transmit stream. The TOSEQ character is put in the Tx FIFO without affecting a Tx buffer in progress. See Section 22.11, “Inserting Control Characters into the Transmit Data Stream.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-4 Freescale Semiconductor...
Page 677 When receiving messages, up to eight control characters can be configured to mark the end of a message or generate a maskable interrupt without being stored in the buffer. This option is useful when flow control MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-5...
Page 678 Resets the receive parameters in the parameter RAM. Should be issued when the receiver is disabled. INIT RX Note that resets both Tx and Rx parameters. PARAMETERS INIT TX AND RX PARAMETERS MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-6 Freescale Semiconductor...
Page 679 (the received control character mask, RCCM) to strip don’t cares. If a match occurs, the received control character can either be written to the receive buffer or rejected. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-7...
Page 680 CHARACTER n Control character values 1–8. Defines control characters to be compared to the 8–15 incoming character. For characters smaller than 8 bits, the most significant bits should be zero. MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-8 Freescale Semiconductor...
Page 681 FIFO. This means that the XON or XOFF character may not be sent for four (SCC2–SCC4) character times. To reduce this latency, set GSMR_H[TFL] to decrease the FIFO size to one character before enabling the transmitter. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-9...
Page 682 For example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones is sent before the first character in the buffer. MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-10 Freescale Semiconductor...
Page 683 The UART receiver can always receive fractional stop bits. The next character’s start bit can begin any time after the three middle samples have been taken. 5–6 — 0b11 7–8 — 0b00 9–14 — 0b111111 — MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-11...
Page 684 If no buffer is open, this event does not generate an interrupt or any status information. The internal idle counter (IDLC) is reset every time a character is received. To disable the idle sequence function, clear MAX_IDL. MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-12 Freescale Semiconductor...
Page 685 SCC UART is in synchronous mode and PSMR[RZS] is set. Fractional stop bits are configured in the DSR. 0 One stop bit 1 Two stop bits MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-13...
Page 686 1 While the SCC is sending data, the internal RTS disables and gates the receiver. Useful for a multidrop configuration in which the user does not want to receive its own transmission. For multidrop UART mode, set the BDs’ preamble bit, TxBD[P]. — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-14 Freescale Semiconductor...
Page 687 ENTER HUNT MODE CLOSE RXBD • An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-15...
Page 688 (MAX_IDL) with this Buffer 10 Characters 5 Characters Long Idle Period Characters Received by UART Fourth Character Present Time has Framing Error! Time Figure 22-7. SCC UART Receiving using RxBDs MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-16 Freescale Semiconductor...
Page 689 PSMR[UM]. After an address match, AM identifies which user-defined address character was matched. 0 The address matched the value in UADDR2 1 The address matched the value in UADDR1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-17...
Page 690 TBASE. The number of TxBDs in this table is determined only by the W bit. Interrupt 0 No interrupt is generated after this buffer is processed. 1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt. MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-18 Freescale Semiconductor...
Page 691 UART mask register (SCCM), which has the same format as SCCE. Setting a mask bit enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 22-10 shows example interrupts that can be generated by the SCC UART controller. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-19...
Page 692 — GRA BRKE BRKS — CCR BSY Reset 0000_0000_0000_0000 Addr 0xA30 (SCCE2)/0xA34 (SCCM2) 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4) Figure 22-11. SCC UART Event Register (SCCE) and Mask Register (SCCM) MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-20 Freescale Semiconductor...
Page 693 Also represents a general receiver error (overrun, CD lost, parity, idle sequence, and framing errors); the RxBD status and control fields indicate the specific error. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-21...
Page 694 INIT RX AND TX PARAMS updates RBPTR and TBPTR of the serial channel with the new values of RBASE and TBASE. 9. Write RFCR with 0x10 and TFCR with 0x10 for normal operation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-22 Freescale Semiconductor...
Page 695 This characteristic is used to impose a message structure on the communication between the devices. For flow control, each device can transmit XON and XOFF characters, which are not part of the program being uploaded or downloaded. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 22-23...
Page 696 XOFF character is received. This scheme minimizes the number of interrupts the core receives (one per S-record) and relieves it from continually scanning for control characters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 22-24 Freescale Semiconductor...
Page 697 Flexible buffers with multiple buffers per frame • Separate interrupts for frames and buffers (Rx and Tx) • Received-frames threshold to reduce interrupt overhead • Can be used with the SCC DPLL MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-1...
Page 698 The HDLC receiver is designed to work with little or no core intervention to perform address recognition, CRC checking, and maximum frame length checking. Received frames can be used to implement any HDLC-based protocol. MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-2 Freescale Semiconductor...
Page 699 BSY condition, but does not include overrun errors. ABTSC (Abort sequence counter) 0x44 RETRC Hword NMARC (Nonmatching address received counter) Includes error-free frames only. RETRC (Frame retransmission counter) Counts number of frames resent due to collision. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-3...
Page 700 HADDR3 0xAA68 HADDR3 0xXX55 HADDR4 0xAA68 HADDR4 0xXX55 Recognizes one 16-bit address (HADDR1) and Recognizes a single 8-bit address (HADDR1) the 16-bit broadcast address (HADDR2) Figure 23-2. HDLC Address Recognition MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-4 Freescale Semiconductor...
Page 701 Resets the Rx parameters in the parameter RAM.; issue only when the receiver is disabled. Note INIT RX that resets both Tx and Rx parameters. PARAMETERS INIT TX AND RX PARAMETERS MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-5...
Page 702 RxBD[AB] and generates a maskable RXF interrupt. The channel also increments the abort sequence counter ABTSC. The CRC and nonoctet error status conditions are not checked on aborted frames. The receiver then enters hunt mode. MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-6 Freescale Semiconductor...
Page 703 10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-7...
Page 704 23-4, to report on data received for each buffer. Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 23-4. SCC HDLC Receive Buffer Descriptor (RxBD) MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-8 Freescale Semiconductor...
Page 705 Because HDLC is a frame-based protocol, RxBD[Data Length] of the last buffer of a frame contains the total number of frame bytes, including the 2 or 4 bytes for CRC. Figure 23-5 shows an example of how RxBDs are used in receiving. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-9...
Page 706 Time Legend: Closing Flag F = Flag A = Address Byte C = Control Byte I = Information Byte CR = CRC Byte Figure 23-5. SCC HDLC Receiving using RxBDs MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-10 Freescale Semiconductor...
Page 707 CTS lost. Indicates when CTS in NMSI mode or layer 1 grant is lost in GCI or IDL mode during frame transmission. If data from more than one buffer is currently in the FIFO when this error occurs, the HDLC writes CT in the current BD after sending the buffer. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-11...
Page 708 It is set no sooner than two clocks after the last bit of the closing flag is received. This event is not maskable via the RxBD[I] bit. Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-12 Freescale Semiconductor...
Page 709 2. Example shows one additional opening flag. This is programmable. 3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself. Figure 23-8. SCC HDLC Interrupt Event Example MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-13...
Page 710 1. Configure port A to enable TXD2 and RXD2. Set PAPAR[12,13] and clear PADIR[12,13] and PAODR[12,13]. 2. Configure port C to enable RTS2, CTS2, and CD2. Set PCPAR[14] and PCSO[8,9] and clear PCPAR[8,9] and PCDIR[8,9,14]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-14 Freescale Semiconductor...
Page 711 25. Write 0x0000 to PSMR2 to configure one opening and one closing flag, 16-bit CCITT-CRC, and prevent multiple frames in the FIFO. 26. Write 0x00000030 to GSMR_L2 to enable the transmitter and receiver. This additional write ensures that ENT and ENR are enabled last. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-15...
Page 712 These protocols handle collisions efficiently because one station can always complete its transmission, at which point, it lowers its own priority to give other devices fair access to the physical connection. MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-16 Freescale Semiconductor...
Page 713 RAM and then resent to the other slave. The benefit of this configuration, however, is that full-duplex operation can be obtained. In a point-to-multipoint environment, this is the preferred configuration. Figure 23-11 shows the single-master configuration. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-17...
Page 714 However, if the received CTS sample is 0 and the transmitted bit is 1, transmission stops after that bit and waits for an idle line before attempting retransmission. Since the HDLC bus uses a MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-18 Freescale Semiconductor...
Page 715 Figure 23-13. TCLK (Output) (Input) CTS sampled at three quarter point. Collision detected when TXD=1, but CTS=0. Figure 23-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-19...
Page 716 As a result, the electrical effects of collisions are isolated locally. Figure 23-15 shows RTS timing. Collision TCLK 1st Bit 2nd Bit 3rd Bit RTS active for only 2 bit times Figure 23-15. Delayed RTS Mode MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-20 Freescale Semiconductor...
Page 717 Set RTE and BUS to 1 • Set BRM to 1 if delayed RTS is desired • Configure CRC to 16-bit CRC CCITT (0b00). • Configure other bits to zero or default. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 23-21...
Page 718 23.14.6.2 HDLC Bus Controller Programming Example Except for the above discussion in Section 23.14.6.1, “Programming GSMR and PSMR for the HDLC Bus Protocol,” use the example in Section 23.13.1, “SCC HDLC Programming Example #1.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 23-22 Freescale Semiconductor...
Page 719 0x01–0x7F are data frames; control byte values from 0x80–0xFF are control frames. Four control frames are defined: • ENQ—Enquiry • ACK—Enquiry acknowledgment • RTS—Request to send a data frame • CTS—Clear to send a data frame MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 24-1...
Page 720 RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector. MPC885 PowerQUICC Family Reference Manual, Rev. 2 24-2 Freescale Semiconductor...
Page 721 LocalTalk synchronization sequence. For example, data frames do not require a preceding synchronization sequence. These bits may be modified on the fly if the AppleTalk protocol is selected. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 24-3...
Page 722 Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 21.2.4, “Transmit-on-Demand Register (TODR).” 24.4.4 SCC AppleTalk Programming Example Except for the previously discussed register programming, use the example in Section 23.13.1, “SCC HDLC Programming Example #1.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 24-4 Freescale Semiconductor...
Page 723 BD and clears TxBD[R]. If TxBD[I] is set, the controller sets SCCE[TXB] so an interrupt can be generated after each buffer, after a group of buffers, or after each frame is sent. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-1...
Page 724 When a condition applies, a two-byte sequence is sent instead of the byte. The sequence consists of the control-escape character (0x7D) followed by the original byte exclusive-ORed with 0x20. MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-2 Freescale Semiconductor...
Page 725 True CHAR=CTRL ESC CHAR=Closing Flag False False XOR_NEXT=1 True CHAR ª 0x20 CHAR=Closing Flag Exit XOR_NEXT=0 False Write CHAR to Buffer End of Frame Exit Abort Figure 25-2. Receive Flowchart MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-3...
Page 726 Program PSMR[CHLN] to 0b11 for proper operation. • Idle characters—When sending, the asynchronous HDLC controller sends idle characters when no data is available; when receiving, it ignores idle characters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-4 Freescale Semiconductor...
Page 727 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Figure 25-3. TXCTL_TBL/RXCTL_TBL MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-5...
Page 728 TxBD. Status line information (CD and CTS) is reported through the port C pins; a maskable interrupt is generated when the status of either line changes. 25.11 Asynchronous HDLC Commands The transmit and receive commands are issued to the CP command register (CPCR). MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-6 Freescale Semiconductor...
Page 729 CTS Lost during The channel stops sending the buffer, closes it, sets SCCE[TXE] and TxBD[CT]. The channel Frame Transmission resumes sending from the next TxBD after a command is issued. RESTART TRANSMIT MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-7...
Page 730 — BRKE BRKS TXE RXF BSY TXB RXB Reset Addr 0xA30 (SCCE2)/0xA34 (SCCM2) 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4) Figure 25-4. Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM) MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-8 Freescale Semiconductor...
Page 731 RXD. The real-time status of CTS and CD is part of the port C parallel I/O. Field — Reset 0000_0000_0000_0000 Addr 0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4) Figure 25-5. SCC Status Register for Asynchronous HDLC Mode (SCCS) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-9...
Page 732 The CPM uses the RxBD, shown in Figure 25-7, to report on received data. An example of the RxBD process is shown in Figure 23-5 Section 23.9, “SCC HDLC Receive Buffer Descriptor (RxBD).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-10 Freescale Semiconductor...
Page 733 Beginning of frame. Set when a frame is closed because a BOF character is received instead of the expected EOF. 10–11 — Reserved, should be cleared. Rx abort sequence. Set when an abort sequence or framing error terminates a frame. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-11...
Page 734 0 Not the last buffer in the current frame. 1 Last buffer in the current frame. The proper CRC and closing flag are sent after the last byte. — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-12 Freescale Semiconductor...
Page 735 TSA or the NMSI. 5. Point RBASE and TBASE in the SCC parameter RAM to the first RxBD and TxBD. 6. Issue the command for the SCC. INIT RX AND TX PARAMETERS MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-13...
Page 736 Figure 25-10.(b). The electrical pulses between the IR transmit encoder and the output driver and LED are of a bit period in duration (or for the slower bit rates, as short as of the bit period for 115.2 Kbps). MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-14 Freescale Semiconductor...
Page 737 3/16 Bit Time Figure 25-10. UART and IR Frames The SIR encoding/decoding is supported only for SCC2. To activate it, set GSMR_L2[SIR] and configure GSMR_L2[RDCR, TDCR] for 16x clock operation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 25-15...
Page 738 SCC Asynchronous HDLC Mode and IrDA MPC885 PowerQUICC Family Reference Manual, Rev. 2 25-16 Freescale Semiconductor...
Page 739 (NMSI). The SCC supports modem lines by connecting to port C pins or general-purpose I/O pins. The controller has separate transmit and receive sections whose operations are asynchronous with the core and either synchronous or asynchronous with other SCCs. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-1...
Page 740 The controller can reset the BCS generator before sending a specific buffer. In transparent mode, the controller inserts a DLE before sending a DLE character, so that only one DLE is used in the calculation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-2 Freescale Semiconductor...
Page 741 DLE–SYNC pair in an underrun condition and stripped from incoming data on receive once the receiver synchronizes to the data using the DSR and SYN1–SYN2 pair. See Section 26.7, “BISYNC SYNC Register (BSYNC).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-3...
Page 742 The controller can inspect data on a per-byte basis and interrupt the core each time a byte is received. • The controller can be programmed so software handles the first two or three bytes. The controller directly handles subsequent data without interrupting the core. MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-4 Freescale Semiconductor...
Page 743 Initializes receive parameters in this serial channel’s parameter RAM to reset state. Issue only when INIT RX the receiver is disabled. An resets transmit and receive parameters. PARAMETERS INIT TX AND RX PARAMETERS MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-5...
Page 744 CHARACTER2 0x46 — CHARACTER3 0x48 — CHARACTER4 0x4A — CHARACTER5 0x4D — CHARACTER6 0x4E — CHARACTER7 0x50 — CHARACTER8 0x52 — MASK VALUE(RCCM) Figure 26-2. Control Character Table and RCCM MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-6 Freescale Semiconductor...
Page 745 (BSYNC[V]) is set.When using 7-bit characters with parity, the parity bit should be included in the SYNC register value. Field SYNC Reset Undefined Addr SCC Base + 0x3E Figure 26-3. BISYNC SYNC (BSYNC) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-7...
Page 746 The BISYNC channel can be programmed to send and receive a synchronization pattern defined in the DSR. GSMR_H[SYNL] defines pattern length, as shown in Table 26-7. The receiver synchronizes on this MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-8 Freescale Semiconductor...
Page 747 CRC checking, the channel closes the buffer, sets the CR bit in the BD, and generates the RXB interrupt if it is enabled. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-9...
Page 748 LRC while in transparent mode. Initialize PRCRC to the CRC16 preset value before setting RTR. Reverse data 0 Normal operation. 1 Any portion of the SCC defined to operate in BISYNC mode operates by reversing the character bit order and sending the msb first. MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-10 Freescale Semiconductor...
Page 749 SCC BISYNC RxBD Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer Offset + 6 Figure 26-6. SCC BISYNC RxBD MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-11...
Page 750 Rx CRC error. Set when this frame contains a CRC error. Received CRC bytes are always written to the receive buffer. Overrun. Set when a receiver overrun occurs during frame reception. Carrier detect lost. Indicates when the carrier detect signal, CD, is negated during frame reception. MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-12 Freescale Semiconductor...
Page 751 0 Send an SYN1–SYN2 or idle sequence (specified in GSMR_H[RTSM]) after the last character in the buffer. 1 Send the BCS sequence after the last character. The controller also resets the BCS generator after sending the BCS. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-13...
Page 752 SCCE bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in the BISYNC mask register (SCCM). SCCE bits are reset by writing ones; writing zeros has no effect. Unmasked bits must be reset before the CP negates the internal interrupt request signal. MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-14 Freescale Semiconductor...
Page 753 The SCC status (SCCS) register allows real-time monitoring of RXD. The real-time status of CTS and CD are part of the port C parallel I/O. Field — — Reset 0000_0000 Addr 0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4) Figure 26-9. SCC Status Registers (SCCS) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-15...
Page 754 Using Table 26-15, the control character table should be set to recognize the end of the block. Table 26-15. Control Characters Control Characters Next entry MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-16 Freescale Semiconductor...
Page 755 8-bit characters. Then write 0xBD20 to TxBD[Status and Control] 0x0005 to TxBD[Data Length], and 0x00002000 to TxBD[Buffer Pointer]. 21. Write 0xFFFF to SCCE to clear any previous events. 22. Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 26-17...
Page 756 Note that after 5 bytes are sent, the TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 26-18 Freescale Semiconductor...
Page 757 IEEE 802.3 frames to coexist on the same LAN, the length field of the frame must always be different from any type fields used in ethernet. This limits the length of the data portion of the frame to 1,500 bytes MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-1...
Page 758 (10BASE-T). The EEST provides a glueless interface to the MPC885, Manchester encoding and decoding, automatic selection of 10BASE-T versus AUI ports, 10BASE-T polarity detection and correction. The MC68160 documentation gives more information. MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-2 Freescale Semiconductor...
Page 759 Up to eight parallel I/O pins can be sampled and appended to any frame • Optional heartbeat indication • Transmitter network management and diagnostics — Lost carrier sense — Underrun MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-3...
Page 760 • Chapter 35, “CPM Interrupt Controller,” defines SCC interrupt priorities and how interrupts are generated to the core. MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-4 Freescale Semiconductor...
Page 761 MPC885 can perform external loop-back testing, which can be controlled by any available MPC885 parallel I/O signal. The passive components needed to connect to MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-5...
Page 762 When the ethernet controller receives a command, it resumes transmission. The ethernet controller sends bytes RESTART TRANSMIT least-significant bit first. MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-6 Freescale Semiconductor...
Page 763 E bit. Then it generates a maskable interrupt, which indicates that a frame has been received and is in memory. The ethernet controller then waits for a new frame. It receives serial data least-significant bit first. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-7...
Page 764 0x52 MAXD Hword Rx max DMA. 0x54 DMA_CNT Hword Rx DMA counter. A temporary down-counter used to track frame length. MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-8 Freescale Semiconductor...
Page 765 The command is used to enable the hash table. SET GROUP ADDRESS 0x98 IADDR3 0x9A IADDR4 0x9C BOFF_CNT Hword Backoff counter. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-9...
Page 766 Initializes transmit parameters in this serial channel parameter RAM to reset state. Issue only when INIT TX the transmitter is disabled. resets both transmit and receive parameters. PARAMETERS INIT TX RX PARAMETERS MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-10 Freescale Semiconductor...
Page 767 In the physical type of address recognition, the ethernet controller compares the destination address field of the received frame with the user-programmed physical address in PADDR1. Address recognition can be performed on multiple individual addresses using the IADDR1–4 hash table. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-11...
Page 768 48-bit address into one GROUP ADDRESS of the 64 bits by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting 6 bits MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-12 Freescale Semiconductor...
Page 769 Data from the transmit FIFO is received immediately into the receive FIFO. There is no heartbeat check in this mode; configure TENA as a general-purpose output. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-13...
Page 770 (DISFC). The receiver then enters hunt mode. Busy A frame was received and discarded because of a lack of buffers. The channel sets SCCE[BSY] and increments DISFC. The receiver then enters hunt mode. MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-14 Freescale Semiconductor...
Page 771 CRC selection. Only CRC = 10 is valid. Complies with ethernet specifications. 32-bit CCITT-CRC. X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-15...
Page 772 The ethernet controller uses the RxBD to report on the received data for each buffer. Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer Offset + 6 Figure 27-6. SCC Ethernet RxBD MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-16 Freescale Semiconductor...
Page 773 PSMR[RSH] is enabled. Late collisions are better defined in PSMR[LCW]. Data length and buffer pointer fields are described in Section 21.3, “SCC Buffer Descriptors (BDs).” Data length includes the total number of frame octets (including four bytes for CRC). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-17...
Page 774 Buffer Pointer 32-Bit Buffer Pointer Still Empty Non-Collided ethernet Frame 1 Line Idle Frame 2 Two Frames Received in ethernet Collision Present Time Time Figure 27-7. Ethernet Receiving Using RxBDs MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-18 Freescale Semiconductor...
Page 775 Heartbeat. Set when the collision input was not asserted within 20 transmit clocks after transmission. HB cannot be set unless PSMR[HBC] = 1. The SCC writes HB after it finishes sending the buffer. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-19...
Page 776 GRACEFUL STOP TRANSMIT 9–10 — Reserved, should be cleared. Set when an error occurs on the transmitter channel. Rx frame. Set when a complete frame has been received on the ethernet channel. MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-20 Freescale Semiconductor...
Page 777 Figure 27-10. Ethernet Interrupt Events Example Note that the SCC status register (SCCS) cannot be used with the ethernet protocol. The current state of the RENA and CLSN signals can be found in port C. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-21...
Page 778 25. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-22 Freescale Semiconductor...
Page 779 Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 27-23...
Page 780 SCC Ethernet Mode MPC885 PowerQUICC Family Reference Manual, Rev. 2 27-24 Freescale Semiconductor...
Page 781 The transparent transmitter is designed to work almost no intervention from the core. When the core enables the SCC transmitter in transparent mode, it starts sending idles, which are logic high or encoded MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 28-1...
Page 782 Similarly, once the SCC receiver is enabled for transparent operation in the GSMR and the RxBD is made empty for the SCC, receive synchronization must occur before data can be MPC885 PowerQUICC Family Reference Manual, Rev. 2 28-2 Freescale Semiconductor...
Page 783 CD of another SCC and to have the data synchronized and bit aligned. It is also an option to link the transmitter synchronization to the receiver synchronization. Diagrams for the pulse/envelope and sampling options are shown in Section 21.4.4, “Controlling SCC Timing with RTS, CTS, and CD.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 28-3...
Page 784 I/O pin in software. • Enable the receiver and transmitter for the SCC in loop-back mode and then change GSMR_L[DIAG] to 0b00 while the transmitter and receiver and enabled. MPC885 PowerQUICC Family Reference Manual, Rev. 2 28-4 Freescale Semiconductor...
Page 785 CRC is calculated as the incoming bits arrive. The optional reversal of data (GSMR_H[REVD] = 1) is done just before data is stored in memory (after the CRC calculation). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 28-5...
Page 786 Initializes all transmit parameters in the serial channel parameter RAM to reset state. Issue only INIT TX when the transmitter is disabled. resets receive and transmit PARAMETERS INIT TX AND RX PARAMETERS parameters. MPC885 PowerQUICC Family Reference Manual, Rev. 2 28-6 Freescale Semiconductor...
Page 787 The protocol-specific mode register (PSMR) is not used by the transparent controller because all transparent mode selections are made in the GSMR. If only half of an SCC (transmitter or receiver) is MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 28-7...
Page 788 RxBD[OV, CD, DE] are set. The transparent controller writes the number of frame octets to the BD’s data length field. 0 Not the last buffer in a frame. 1 Last buffer in a frame. MPC885 PowerQUICC Family Reference Manual, Rev. 2 28-8 Freescale Semiconductor...
Page 789 CPM after the buffer is sent. Offset + 0 — — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer Offset + 6 Figure 28-3. SCC Transparent Transmit Buffer Descriptor (TxBD) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 28-9...
Page 790 Event bits are reset by writing ones; writing zeros has no effect. All unmasked bits must be reset before the CPM negates the internal interrupt request signal. Figure 28-4 shows the event and mask registers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 28-10 Freescale Semiconductor...
Page 791 The SCC status register (SCCS) allows monitoring of real-time status conditions on the RXD line. The real-time status of CTS and CD are part of the port C parallel I/O. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 28-11...
Page 792 10. Write MRBLR with the maximum number of bytes per receive buffer and assume 16-bytes, so MRBLR = 0x0010. 11. Write CRC_P with 0x0000_FFFF to comply with the 16-bit CRC-CCITT. 12. Write CRC_C with 0x0000_F0B8 to comply with the 16-bit CRC-CCITT. MPC885 PowerQUICC Family Reference Manual, Rev. 2 28-12 Freescale Semiconductor...
Page 793 Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 28-13...
Page 794 SCC Transparent Mode MPC885 PowerQUICC Family Reference Manual, Rev. 2 28-14 Freescale Semiconductor...
Page 795 FIFO size (latency) of two characters. Figure 29-1 shows the SMC block diagram. SYNC Control Control Registers Logic Peripheral Bus Data Data Register Register Shifter Shifter Figure 29-1. SMC Block Diagram MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-1...
Page 796 Figure 29-2, select the SMC mode as well as mode-specific parameters. The functions of SMCMR[8–15] are the same for each protocol. SMCMR[0–7] vary according to the protocol selected by SMCMR[SM]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-2 Freescale Semiconductor...
Page 797 0 One stop bit. 1 Two stop bits. — Reserved, should be cleared (transparent) Monitor enable. (GCI) 0 The SMC does not support the monitor channel. 1 The SMC supports the monitor channel. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-3...
Page 798 In UART and transparent modes, the SMC memory structure is like the SCC in that SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized in a BD table located in the dual-port RAM. See Figure 29-3. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-4 Freescale Semiconductor...
Page 799 SMC parameter RAM are discussed in the sections that follow. The SMC parameter RAM shared by the UART and transparent protocols is shown in Table 29-2. Parameter RAM for GCI protocol is described in Section 29.5.1, “SMC GCI Parameter RAM.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-5...
Page 800 A down-count value initialized with the TxBD data length and decremented with every byte the SDMA channels read. 0x24 — Word Tx temp. Can be used only by the CP. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-6 Freescale Semiconductor...
Page 801 AT[1–3] Address type 1–3. Contains the user-defined function code value used during the SDMA channel memory access. AT[0] is always driven high to identify this channel access as a DMA-type access. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-7...
Page 802 2. CLOSE RXBD INIT RX PARAMETERS 4. Set SMCMR[REN]. Reception immediately uses the RxBD that RBPTR points to if E is set in that RxBD. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-8 Freescale Semiconductor...
Page 803 • Built-in multidrop modes • Freeze mode for implementing flow control • Isochronous operation (1× clock) (That is, a 16× clock is required.) • Interrupts on special control character reception MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-9...
Page 804 1 stop bit, character length is 10 bits. 0x2A IDLC Hword Temporary idle counter. Down-counter in which the CP stores the current idle counter value in the MAX_IDL time-out process. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-10 Freescale Semiconductor...
Page 805 BD, and, if it is empty, continues transferring data to this BD’s buffer. If CM is set in the RxBD, the E bit is not cleared, so the CP can overwrite this buffer on its next access. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-11...
Page 806 Initializes receive parameters in this serial channel parameter RAM to reset state. Issue it only if the INIT RX receiver is disabled. resets both receive and transmit parameters. PARAMETERS INIT TX AND RX PARAMETERS MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-12 Freescale Semiconductor...
Page 807 BRKLN. If the channel was processing a buffer when the break was received, the buffer is closed with the BR bit in the RxBD set. The RX interrupt is generated if it is enabled. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-13...
Page 808 Buffer closed on reception of idles. Set when the buffer has closed because a programmable number of consecutive idle sequences is received. The CP writes ID after received data is in the buffer. 8–9 — Reserved, should be cleared MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-14 Freescale Semiconductor...
Page 809 RxBDs are used in receiving 10 characters, an idle period, and five characters (one with a framing error). The example assumes that MRBLR = 8. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-15...
Page 810 (MAX_IDL) with this Buffer 10 Characters 5 Characters Long Idle Period Characters Received by UART Fourth Character Present Time has Framing Error! Time Figure 29-7. SMC UART Receiving using RxBDs MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-16 Freescale Semiconductor...
Page 811 If there are more than 8 bits in the UART character, data length should be even. For example, to transmit three UART characters of 8-bit data, 1 start, and 1 stop, initialize the data length field MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-17...
Page 812 Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the middle of the last stop bit of the last character that is written to the receive buffer. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-18 Freescale Semiconductor...
Page 813 9. Write MAX_IDL with 0x0000 in the SMC UART-specific parameter RAM to disable the MAX_IDL functionality for this example. 10. Clear BRKLN and BRKEC in the SMC UART-specific parameter RAM. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-19...
Page 814 Can transmit and receive transparently on its own set of pins using a sync pin to synchronize the beginning of transmission and reception to an external event • Programmable character length (4–16) MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-20 Freescale Semiconductor...
Page 815 BD’s buffer. If the CM bit is set in the RxBD, the E bit is not cleared, so the CP can automatically overwrite the buffer on its next access. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-21...
Page 816 Glitches on SMSYN can cause erratic behavior of the SMC. The transmitter and receiver never lose synchronization again, regardless of the state of SMSYN, until the TEN bit is cleared or an command is issued. ENTER HUNT MODE MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-22 Freescale Semiconductor...
Page 817 The TSA allows the SMC receiver and transmitter to be enabled simultaneously and synchronized separately; SMSYN does not provide this capability. Figure 29-12 shows synchronization using the TSA. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-23...
Page 818 If a buffer is made ready after its SMC is enabled, the first byte can appear in any time slot associated with this channel. • If a buffer is closed with BD[L] set, then the next buffer can appear in any time slot associated with this channel. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-24 Freescale Semiconductor...
Page 819 Initializes receive parameters in this serial channel to reset state. Use only if the receiver is disabled. NIT RX command resets receive and transmit parameters. PARAMETERS INIT TX AND RX PARAMETERS MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-25...
Page 820 1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the core should not write any fields of this RxBD. — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-26 Freescale Semiconductor...
Page 821 SMC transparent TxBD format. Offset + 0 — — — — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer Offset + 6 Figure 29-14. SMC Transparent Transmit BD (TxBD) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-27...
Page 822 8 bits, in which case the transmit buffer pointer must be even. For instance, the pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters must be even. The buffer can reside in internal or external memory. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-28 Freescale Semiconductor...
Page 823 TSA. These alternate functions cannot be used on this pin. 3. Connect CLK3 to SMC1 using the SI. Clear SIMODE[SMC1] and set SIMODE[SMC1CS] to 0b110. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-29...
Page 824 3. Initialize the SDCR to 0x0001. 4. Write RFCR and TFCR with 0x10 for normal operation. 5. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16 bytes, so MRBLR = 0x0010. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-30 Freescale Semiconductor...
Page 825 Width Description 0x00 M_RxBD Hword Monitor channel RxBD. See Section 29.5.5, “SMC GCI Monitor Channel RxBD.” 0x02 M_TxBD Hword Monitor channel TxBD. See Section 29.5.6, “SMC GCI Monitor Channel TxBD.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-31...
Page 826 SMC GCI C/I Channel Transmission Process The core writes the data byte into the C/I TxBD and the SMC transmits the data continuously on the C/I channel to the physical layer device. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-32 Freescale Semiconductor...
Page 827 Data mismatch. Set when two different consecutive bytes are received; cleared when the last two consecutive bytes match. The SMC waits for the reception of two identical consecutive bytes before writing new data to the RxBD. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-33...
Page 828 29-18, is used by the CP to report on the C/I channel receive byte. The RxBD itself receives the C/I data. Offset + 0 — C/I Data — Figure 29-18. SMC C/I Channel RxBD MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-34 Freescale Semiconductor...
Page 829 SMCM bit disables, the corresponding interrupt Unmasked bits must be cleared before the CP clears the internal interrupt request to the CP interrupt controller (CPIC). Figure 29-20 shows the SMCE/SMCM register format. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 29-35...
Page 830 CRXB C/I channel buffer received. Set when the C/I receive buffer becomes full. MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer becomes empty. MRXB Monitor channel buffer received. Set when the monitor receive buffer becomes full. MPC885 PowerQUICC Family Reference Manual, Rev. 2 29-36 Freescale Semiconductor...
Page 831 The following is a list of the SPI’s main features: • Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL) • Full-duplex operation • Works with data characters from 4 to 16 bits long • Supports back-to-back character transmission and reception MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-1...
Page 832 B[28–31] signals, respectively. They are configured as SPI signals through the port B signal assignment register (PBPAR) and the Port B data direction register (PBDIR), specifically by setting PBPAR[DDn] and PBDIR[DRn]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-2 Freescale Semiconductor...
Page 833 RxBDs. The core then sets SPCOM[STR] in the SPI command register to start sending data, which starts once the SDMA channel loads the Tx FIFO with data. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-3...
Page 834 SPI event register and a maskable interrupt is issued to the core. It also disables SPI operation and the output drivers of SPI signals. The core must clear SPMODE[EN] before the SPI is used again. After correcting the problems, clear SPIE[MME] and reenable the SPI. MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-4 Freescale Semiconductor...
Page 835 • It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example) • SELOUTx signals are implemented in software with general-purpose I/O signals Figure 30-3. Multimaster Configuration MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-5...
Page 836: Spi Registers
0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not functioning and the input clock is disabled. 1 The SPI is enabled. MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-6 Freescale Semiconductor...
Page 837 (SPMODE[CP] = 1). SPICLK (CI = 0) SPICLK (CI = 1) SPIMOSI (From Master) SPIMISO (From Slave) SPISEL Note: Q = Undefined Signal Figure 30-6. SPI Transfer Format with SPMODE[CP] = 1 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-7...
Page 838 Setting a bit in the SPI mask register (SPIM) enables and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared before the CPM clears internal interrupt requests. Figure 30-7 shows both registers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-8 Freescale Semiconductor...
Page 839 Tx data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is asserted. STR is cleared automatically after one system clock cycle. 1–7 — Reserved and should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-9...
Page 840 Tx buffer is in use. 0x22 — Hword The Tx internal byte count is a down-count value initialized with TxBD[Data Length]and decremented with every byte read by the SDMA channels. MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-10 Freescale Semiconductor...
Page 841 AT[1–3] Address type 1–3. Contains the user-defined function code value used during the SDMA channel memory access. AT0 is always driven high to identify this channel access as a DMA-type access. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-11...
Page 842 30-12, has the following structure: • The half word at offset + 0 contains status and control bits. The CPM updates the status bits after the buffer is sent or received. MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-12 Freescale Semiconductor...
Page 843 1 The buffer is empty or reception is in progress. The CPM owns this RxBD and its buffer. Once E is set, the core should not write any fields of this RxBD. — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-13...
Page 844 TxBD fields should be prepared before data is sent. The format of an TxBD is shown in Figure 30-12. Offset + 0 — — — Offset + 2 Data Length Offset + 4 Tx Buffer Pointer Offset + 6 Figure 30-12. SPI Transmit BD (TxBD) MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-14 Freescale Semiconductor...
Page 845 PBDIR[31] and by clearing PBODR[31]. 2. Configure a parallel I/O signal to operate as the SPI select output signal if needed. If PB156 is chosen, clear PBODR[156] and PBPAR[156] and set PBDIR[156]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-15...
Page 846 0x0051 to CPCR. INIT RX AND TX PARAMETERS 5. Write 0x0001 to SDCR. 6. Set MRBLR = 0x0010 for 16 bytes, the maximum number of bytes per buffer. MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-16 Freescale Semiconductor...
Page 847 2. Process the TxBD to reuse it and the RxBD to extract the data from it. To transmit another buffer, simply set TxBD[R], RxBD[E], and SPCOM[STR]. 3. Clear the interrupt by writing a one to CISR[SPI]. 4. Execute an rfi instruction. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 30-17...
Page 848 Serial Peripheral Interface (SPI) MPC885 PowerQUICC Family Reference Manual, Rev. 2 30-18 Freescale Semiconductor...
Page 849 Four independent endpoints support control, bulk, interrupt, and isochronous data transfers • CRC16 generation and checking • CRC5 checking • NRZI encoding/decoding with bit stuffing • 12- or 1.5-Mbps data rate MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-1...
Page 850 31-1, the USB controller interfaces to the USB bus through a differential line driver and differential line receiver. The OE (output enable) signal enables the line driver when the USB controller transmits on the bus. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-2 Freescale Semiconductor...
Page 851 Outputs from the USB transmitter, inputs to the differential driver. USBTXP Result single ended “0” logic “0” logic “1” — USBOE Output enable. Enables the transceiver to send data on the bus. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-3...
Page 852 The USB transmitter contains four independent FIFOs, each containing 16 bytes. There is a dedicated FIFO for each of the four supported endpoints. The USB receiver has a single 16-byte FIFO. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-4 Freescale Semiconductor...
Page 853 USB controller for each token. Tokens that are not valid (i.e PID check fails or CRC check fails or packet length is not 3 bytes) are ignored by the USB controller. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-5...
Page 854 RxBD associated with this packet. USB Out Token Reception USEP n [RHS] Data Packet Corrupted Handshake Sent to Host None (Data Discarded) 00 (Normal) 01 (Ignore) None 10 (NAK) 11 (STALL) STALL MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-6 Freescale Semiconductor...
Page 855 The USB transmitter contains four independent FIFOs, each containing 16 bytes. Endpoint 0 is dedicated for host transactions, endpoints 1-3 are for function transactions in test mode. There is a MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-7...
Page 856 Once enabled, the USB host controller waits for a packet in its FIFO. When the FIFO is filled with a packet, the host transaction starts. Figure 31-3 Table 31-2 describe the behavior of the USB host MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-8 Freescale Semiconductor...
Page 857 Endpoints 1-3 receive/transmit data according to tokens received from host. The programming model and functional description are as described in Section 31.11, “USB Function Programming Model.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-9...
Page 858 The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID. A SETUP token is recognized only by a control endpoint and cannot be answered with nak or stall, there for host expects either ack or no handshake at all. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-10 Freescale Semiconductor...
Page 859 31-7, begins at the USB base address, 0x1C00 (offset from RAM_Base). The user must initialize certain parameter RAM values before the USB controller is enabled. Other values are initialized by the CP. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-11...
Page 860 (EPxPTR) is shown in Figure 31-8. Field Endpoint Index Pointer — Reset 0000_0000_0000_0000 Addr USB base + 0x00 (EP0PTR), 0x02 (EP1PTR), 0x04 (EP2PTR), 0x06 (EP3PTR) Figure 31-8. Endpoint Pointer Registers (EP x PTR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-12 Freescale Semiconductor...
Page 861 16 bits Transmit internal byte count. A down-count value that is initialized with the TxBD data length and decremented with every byte read by the SDMA channels. 0x18 TTEMP 32 bits Tx temp MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-13...
Page 862 The entry is updated by the application software whenever a SOF (start of frame) token should be received. The software should prepare the frame number and the crc and place it in FRAME_N field. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-14 Freescale Semiconductor...
Page 863 SDMA channel accesses memory, as well as the required byte ordering for the data buffer. Figure 31-11 shows the USB function code registers. Field — Figure 31-11. USB Function Code Registers (RFCR and TFCR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-15...
Page 864 The USMOD register controls the USB controller operation mode. Figure 31-12 shows the USMOD register. Field RESUME — SFTE TEST HOST Reset 0000_0000 Addr 0xA00 Figure 31-12. USB Mode Register (USMOD) MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-16 Freescale Semiconductor...
Page 865 Table 31-9. USADR Fields Bits Name Description — Reserved, should be cleared. 1–7 SAD x Slave address 0–6. Holds the slave address for the USB port, when configured as a function MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-17...
Page 866 If it is not, retransmission should be handled by software intervention. Note: Should be set to zero for endpoint which is configured for ISO transfer mode MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-18 Freescale Semiconductor...
Page 867 Stop_Tx command. After flushing the FIFO the user should issue the Restart_Tx command (Refer to Section 31.13, “USB CP Commands.”). FLUSH is always read as a zero. 2–5 — Reserved, should be cleared. 6–7 Endpoint. Selects one of the four supported endpoints. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-19...
Page 868 If a bit in the USBMR is one, the corresponding interrupt in the USBER is enabled. If the bit is zero, the corresponding interrupt in the USBER will be masked. This register is cleared at reset. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-20 Freescale Semiconductor...
Page 869 The CP confirms reception and transmission or indicates error conditions using the BDs to inform the processor that the buffers have been serviced. The buffers may reside in either external memory or internal memory. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-21...
Page 870 EP0 RxBD TABLE POINTER EP0 TxBD TABLE POINTER FRAME STATUS DATA LENGTH RX DATA BUFFER EP3 RxBD DATA POINTER TABLE POINTER EP3 TxBD TABLE POINTER Figure 31-18. USB Memory Structure MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-22 Freescale Semiconductor...
Page 871 BD in the table (the BD pointed to by RBASE). The number of RxBDs in this table is programmable and is determined only by the W-bit and the overall space constraints of the dual-port RAM. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-23...
Page 872 4. The buffer may reside in either internal or external memory pointer Data length represents the number of octets that the CP has written into this BD’s buffer. It is written once by the CP as the BD is closed. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-24 Freescale Semiconductor...
Page 873 0 Transmit end-of-packet after the last data byte. This setting can be used for testing purposes to send a bad CRC after the data. 1 Transmit the CRC sequence after the last data byte. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-25...
Page 874 TX DATA BUFFER POINTER OFFSET + 6 Figure 31-21. USB Transmit Buffer Descriptor (TxBD) Entries in boldface must be initialized by the user. All fields should be prepared by the user before transmission. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-26 Freescale Semiconductor...
Page 875 Packet ID. This bit field is valid for the first BD of a packet; otherwise it is ignored. 0X Do not append PID to the data. 10 Transmit DATA0 PID before sending the data. 11 Transmit DATA1 PID before sending the data. — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-27...
Page 876 This command enables the transmission of data from the corresponding endpoint on the USB. This command is expected by the USB controller after a STOP Tx Command, or after transmission error (underrun or time-out). MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-28 Freescale Semiconductor...
Page 877 In isochronous mode (USEP n [TM] = 0b11), the USB controller reports a CRC error; however, there are no handshake packets (ACK) and the transfer continues normally when an error occurs. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-29...
Page 878 23. Clear the TSTATE field of the endpoint 0 parameter RAM. 24. Write 0x2008_2028 to DPRAM+0x520 to set up the RBASE and TBASE fields of the endpoint 1 parameter RAM. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-30 Freescale Semiconductor...
Page 879 31.16 Programming the USB Host Controller The MPC885 implementation of a USB host uses endpoint 0 to control the host transmission and reception. The other endpoints are typically not used, unless for testing purposes (loop-back). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-31...
Page 880 14. Write 0x698560 to DPRAM+0x200 to set up the endpoint 0 Tx data pattern. This pattern consists of the IN token and the CRC5. 15. Write 0xABCD_1234 to DPRAM+0x210 to set up the endpoint 1 Tx data pattern. MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-32 Freescale Semiconductor...
Page 881 • RxBD[Status and Control] of endpoint 0 should contain 0x3C00. • RxBD[Data Length] of endpoint 0 should contain 0x0005. • The receive buffer of endpoint 0 should contain 0xABCD_122B, 0x42xx_xxxx. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 31-33...
Page 882 Universal Serial Bus (USB) MPC885 PowerQUICC Family Reference Manual, Rev. 2 31-34 Freescale Semiconductor...
Page 883 FIFO latency. In normal operation, the msb (bit 0) is shifted out first. When the I C is not enabled in the C mode register (I2MOD[EN] = 0), it consumes little power. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 32-1...
Page 884 C controller sends a message specifying a read or write request to an I slave. The first byte of the message consists of a 7-bit slave port address and a R/W request bit. Note that MPC885 PowerQUICC Family Reference Manual, Rev. 2 32-2 Freescale Semiconductor...
Page 885 If the MPC885 is the slave target of the write, prepare receive buffers and BDs to await the master’s request. Figure 32-4 shows the timing for a master write. Data Byte Device Address Note: Data and ACK are repeated n times. Figure 32-4. I C Master Write Timing MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 32-3...
Page 886 1. Set the master’s I2COM[STR] to initiate the read. The transfer starts when the SDMA channel loads the transmit FIFO with data and the I C bus is not busy. 2. The slave detects a start condition on SDA and SCL. MPC885 PowerQUICC Family Reference Manual, Rev. 2 32-4 Freescale Semiconductor...
Page 887 (which register should be read, for example). This operation is typical with many I C devices. 32.4 C Registers The following sections describe the I C registers. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 32-5...
Page 888 C operation. C is disabled. The I C is in a reset state and consumes minimal power. C is enabled. Do not change other I2MOD bits when EN is set. MPC885 PowerQUICC Family Reference Manual, Rev. 2 32-6 Freescale Semiconductor...
Page 889 C controller sets the corresponding I2CER bit. I2CER bits are cleared by writing ones—writing zeros has no effect. Setting a bit in the I C mask register (I2CMR) enables and clearing a MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 32-7...
Page 890 Tx data register from the current Tx buffer (if ready) and start sending when it receives an address byte that matches the slave address with R/W = 1. STR is always read as a 0. MPC885 PowerQUICC Family Reference Manual, Rev. 2 32-8 Freescale Semiconductor...
Page 891 0x12 RCOUNT Hword Rx internal byte count is a down-count value that is initialized with the MRBLR value and decremented with every byte the SDMA channels write. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 32-9...
Page 892 AT[1–3] Address type 1–3. Contains the user-defined function code value used during the SDMA channel memory access. AT0 is always driven high to identify this channel access as a DMA-type access. MPC885 PowerQUICC Family Reference Manual, Rev. 2 32-10 Freescale Semiconductor...
Page 893 I2C RxBD Table RxBD Table Rx Buffer Status and Control I2C RxBD Table Pointer Data Length (RBASE) Buffer Pointer I2C TxBD Table Pointer (TBASE) Figure 32-12. I C Memory Structure MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 32-11...
Page 894 1 The buffer is empty or reception is in progress. The CPM owns this RxBD and its buffer. Once E is set, the core should not write any fields of this RxBD. — Reserved and should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 32-12 Freescale Semiconductor...
Page 895 1 Last BD in the table. After this buffer is used, the CPM transmits data using the BD pointed to by TBASE (top of the table). The number of BDs in this table is determined only by the W bit. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 32-13...
Page 896 C controller updates UN after the buffer is sent. Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating for the bus. The I C controller updates CL after the buffer is sent. MPC885 PowerQUICC Family Reference Manual, Rev. 2 32-14 Freescale Semiconductor...
Page 897 Transparent I/O using a single strobe • Programmable handshake timing attributes • Supports the Centronics receiver/transmitter interface • Supports fast connection between MPC8xx family devices • Can be controlled by the core or CP MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-1...
Page 898 Data is prepared by the core using PIP buffer descriptors. CP-controlled strobed transfers are the same as core-controlled transfers described above, except reads and writes to PBDAT are done automatically by MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-2 Freescale Semiconductor...
Page 899 Tx buffer is in use. 0x22 T_CNT Hword Tx internal byte count 0x24 TTEMP Word Tx temporary From PIP base address. PIP base = IMMR + 0x3F80 (SMC2) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-3...
Page 900 If the core controls the transmitter, the masking function can be performed in software by reading the individual status signals for errors. When receiving, core software drives the status signals using general-purpose outputs. Field Addr PIP base + 0x05 Figure 33-3. Status Mask Register (SMASK) MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-4 Freescale Semiconductor...
Page 901 CP initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but it can be updated if the receiver is disabled or if no Rx buffer is in use. 0x12 R_CNT Hword Rx internal byte count MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-5...
Page 902 PIPE. The rejection method allows the user to handle control characters that are not part of the received message. The PIP receiver uses the structure shown in Figure 33-4 to support control character recognition. MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-6 Freescale Semiconductor...
Page 903 0 Ignore this bit when comparing the incoming character to CHARACTER n . 1 Use this bit when comparing the incoming character to CHARACTER n . MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-7...
Page 904 SBSY Set BUSY. When SBSY is set, BUSY is driven high. SBSY is automatically cleared after the PIP asserts BUSY. Set EBSY before using SBSY or CBSY. Note that PIPC[T/R] should be cleared (receiving) if SBSY or CBSY are used. MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-8 Freescale Semiconductor...
Page 905 PIP mask register (PIPM). Writing ones to the PIPE bits clears the events; writing zeros has no effect. All unmasked flags must be cleared before the CP clears internal interrupt requests. Figure 33-6 shows the register format. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-9...
Page 906 The PIP timing parameters register (PTPR) holds two timing parameters, TPAR1 and TPAR2, used in the pulsed handshake modes for both sending and receiving. See Section 33.7.2.2, “Pulsed Handshake Timing.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-10 Freescale Semiconductor...
Page 907 Port B data register (PBDAT) register functions as the PIP data register when the PIP is used. Use this register to receive or transmit PIP data when the PIP is controlled by core software. See Section 34.3.1.2, “Port B Data Register (PBDAT).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-11...
Page 908 The CP clears R after the buffer is sent or an error is encountered. 1 The buffer is ready for sending or is being sent. No fields of this BD can be written while R = 1. — Reserved, should be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-12 Freescale Semiconductor...
Page 909 Figure 33-10. PIP Rx Buffer Descriptor (RxBD) Table 33-10 describes the PIP RxBD status and control field. The data length and buffer pointer are described in Section 33.5, “PIP Buffer Descriptors,” above. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-13...
Page 910 Initializes all transmit parameters in the PIP parameter RAM to their reset state and should be issued only INIT TX when the transmitter is disabled. PARAMETERS The PIP receive commands are described in Table 33-12. MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-14 Freescale Semiconductor...
Page 911 ACK is asserted and then negated after the data is removed from the input latch. Figure 33-11 shows the handshake timing of the interlocked mode. Setup Hold Transmitter Data Transmitter (Output Ready) Receiver (Input Ready) Figure 33-11. Interlocked Handshake Mode Timing MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-15...
Page 912 (PIPC) register. When the PIP is under CP control, timing attributes are set in PTPR. Transmit and receive errors are reported through BDs. For information about supporting a Centronics interface, see Section 33.9, “Implementing Centronics.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-16 Freescale Semiconductor...
Page 913 Timing Parameters Register (PTPR).” Figure 33-14 shows how the timing parameter TPAR1 governs the setup time and TPAR2 defines the pulse width of STB of a PIP transmitter using pulsed handshake mode timing. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-17...
Page 914 BUSY (PB31) TPAR1 TPAR2 Figure 33-15. PIP Receiver Timing—Mode 0 BUSY (PB31) TPAR1 TPAR2 Figure 33-16. PIP Receiver Timing—Mode 1 BUSY (PB31) TPAR1 TPAR2 Figure 33-17. PIP Receiver Timing—Mode 2 MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-18 Freescale Semiconductor...
Page 915 IEEE P1284 allow bidirectional transfers. With software to allow switching between receive and transmit modes, the PIP can support bidirectional transfers, but does not fully comply with the full-duplex P1284 standard interface. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-19...
Page 916 Strobe pulse width and setup time parameters are set in the PIP timing parameters register (PTPR). Note that one data frame can span several buffers with a maskable interrupt generated after each BD is processed. MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-20 Freescale Semiconductor...
Page 917 Rx buffer or rejected, depending on the reject bit in the control character table. If rejected, the character is written to the received control character register (RCCR) in the PIP Rx parameter RAM and a maskable MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 33-21...
Page 918 The relevant PIPE event bits for Centronics receiving are CCR, BSY, RCH, and RXB; see Section 33.4.2, “PIP Event Register (PIPE).” For core-controlled receiving, only the character-based RCH interrupt applies. MPC885 PowerQUICC Family Reference Manual, Rev. 2 33-22 Freescale Semiconductor...
Page 919 MPC885 applications. To understand signal assignments described in this chapter, it helps to understand each CPM peripheral. Note that the FEC1-MII interface uses also I/O signals that are not part of the ports I/O: • MII1_CRS • MII1_MDIO • MII1_TX_EN • MII1_COL MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-1...
Page 920 — — PA13 PORT A13 RXD2 — PA12 PORT A12 TXD2 — — PA11 PORT A11 RXD4 MII1-TXD0 RXD4 = GND RMII1-TXD0 PA10 PORT A10 TIN4/CLK7 MII1-TXER TIN4/CLK7 = BRG04 MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-2 Freescale Semiconductor...
Page 921 The port A open-drain register (PAODR), shown in Figure 34-1, determines which port signals with serial channel output capability are configured in a normal or wired-OR configuration. Setting the PAODR bits configure the signals for open-drain operation. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-3...
Page 922 Port A data direction register (PADIR) bits configure port A signals as general-purpose inputs or outputs. If a signal is not programmed for general-purpose I/O, PADIR selects the peripheral function to be performed. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-4 Freescale Semiconductor...
Page 923 PA15 can be configured as a general-purpose I/O signal but not as an open-drain signal. It can also be USBRXD for the USB. If it is configured as a general-purpose I/O signal, the RXD1 input is internally grounded. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-5...
Page 924 Figure 34-5. Block Diagram for PA15 (True for all Non-Open-Drain Port Signals) Using PA14 as an example, Figure 34-6 shows the functional block diagram for all port A signals with open-drain capability. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-6 Freescale Semiconductor...
Page 925 UTOPIA multi-PHY operations use port B for RxAddr [4:0] and TxAddr [4:0] signals.The number of active PHY address signals is programmed in UTMODE; for further information see “UTOPIA Mode Register (UTMODE)” in Chapter 43, “UTOPIA Interface.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-7...
Page 926 Port B15 – TxClav BRG03 RxClav — PB14 Port B14 – RxAddr[2] TxAddr[2] — UT = PDPAR[UT] In Slave Mode, the UTOPIA signals are named from the UTOPIA Master’s perspective. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-8 Freescale Semiconductor...
Page 927 PBDAT can be read or written at any time and is not initialized. This register is affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-9...
Page 928 Reset R/W R/W Addr 0xABA Figure 34-9. Port B Data Direction Register (PBDIR) This register is affected by HRESET but is not affected by SRESET. Table 34-9 describes PBDIR bits. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-10 Freescale Semiconductor...
Page 929 Port C Port C consists of 12 general-purpose I/O signals that can generate interrupts, which are managed by the CPM interrupt controller (CPIC). Table 34-11 lists port C signal options. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-11...
Page 930 1. Write the corresponding PCPAR bit with a 0. 2. Write the corresponding PCDIR bit with a 1. 3. Write the corresponding PCSO bit with a zero (for clarity). 4. The corresponding PCINT bit is a ‘don’t care.’ MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-12 Freescale Semiconductor...
Page 931 5. Write the corresponding CIMR bit with a 1 so that interrupts can be sent to the core. 6. The signal value can be read at any time using the PCDAT register. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-13...
Page 932 Port C data direction register (PCDIR) bits configure port C signals as general-purpose inputs or outputs. If a signal is not programmed for general-purpose I/O, PCDIR, along with PCSO, selects the peripheral function to be performed. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-14 Freescale Semiconductor...
Page 933 0 General-purpose I/O. The peripheral functions of the signal are not used. 1 Dedicated peripheral function. The signal is used by the internal module. The on-chip peripheral function to which it is dedicated can be determined by other bits. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-15...
Page 934 PCINT bits 1 PC11 functions as USBRXP, provided that bits PCDIR[11] and PCPAR[11] are zero. In addition, this pin is a general-purpose interrupt pin MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-16 Freescale Semiconductor...
Page 935 Dedicated on-chip peripheral signal (PDPAR[DDn] = 1) PDPAR and the port D data direction register (PDDIR) are cleared at reset, thus configuring all port D signals as general-purpose input signals. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-17...
Page 936 A read of the port D data (PDDAT) register returns the value of the signal, regardless of whether it is an input or output. This allows output conflicts to be found on the signal by comparing the written data with MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-18 Freescale Semiconductor...
Page 937 Port D data direction. Configures port D signals as inputs or outputs when functioning as general-purpose I/O. 0 The corresponding signal is an input. 1 The corresponding signal is an output. PD8 and PD10 will function as open drain. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-19...
Page 938 If a port E signal is configured as an output, the output latch data is gated onto the port signal. When PEDAT is read, the port signal itself is read. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-20 Freescale Semiconductor...
Page 939 SMSYN1 =PB23 PE16 Port E16 L1RCLKB/ TXD3 MII2-TXCLK — CLK6 RMII2-REFCLK PE15 Port E15 — — TGATE1 MII2-TXD1 TGATE1=PC10 RMII2-TXD1 PE14 Port E14 — — RXD3 MII2-TXD0 RXD3 =PD11 RMII2-TXD0 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-21...
Page 940 PEDAT is latched; if the corresponding PEDIR bit is configured as an output, the latched value is driven onto its respective signal. PEDAT can be read or written at any time and is not initialized. This register is affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-22 Freescale Semiconductor...
Page 941 Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31 Reset R/W R/W Addr 0xACA Figure 34-21. Port E Data Direction Register (PEDIR) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-23...
Page 942 1 Dedicated peripheral function. The signal is used by the internal module. The on-chip peripheral function to which it is dedicated can be determined by other bits such as those in the PEDIR and PESO. MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-24 Freescale Semiconductor...
Page 943 Port E Special Options. If the port E signal is configured as peripheral function, the SO bit configures further the on-chip peripheral 0 Select the signals for the first choice of the on-chip peripheral 1 Select the signals for the second choice of the on-chip peripheral MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 34-25...
Page 944 Parallel I/O Ports MPC885 PowerQUICC Family Reference Manual, Rev. 2 34-26 Freescale Semiconductor...
Page 945 MPC8xx core. For information about the SIU interrupt structure, see Section 10.5.1, “Interrupt Structure.” information about the external interrupt exception, see Section 6.1.2.5, “External Interrupt Exception (0x00500).” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 35-1...
Page 946 CPM Interrupt Source Priorities The CPIC has 29 interrupt sources that assert a single programmable interrupt request level to the core. Default interrupt priorities are as shown in Table 35-1. MPC885 PowerQUICC Family Reference Manual, Rev. 2 35-2 Freescale Semiconductor...
Page 947 If SPS = 1, the USB and 3 SCCs are grouped at the top of the priority table, ahead of most other CPM interrupt sources. Grouping is useful where the USB and 3 SCCs function at a very high data rate and interrupt latency is critical. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 35-3...
Page 948 (such as the SMC UART register (SMCM), described in Section 29.3.12, “SMC UART Event Register (SMCE)/Mask Register (SMCM)”). Table 35-2 shows the interrupt sources that have multiple interrupting events. Figure 35-2 shows masking using the SMC sub-block. MPC885 PowerQUICC Family Reference Manual, Rev. 2 35-4 Freescale Semiconductor...
Page 949 0x0F Parallel I/O—PC11 01111 0x1E 11110 0x0E Parallel I/O—PC10 01110 0x1D SCC2 11101 0x0D Reserved 01101 0x1C SCC3 11100 0x0C Timer 3 01100 0x1B SCC4 11011 0x0B Parallel I/O—PC9 01011 MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 35-5...
Page 950 Note that the names and placement of bits is identical in the CIPR, CIMR, and CISR. 35.5.1 CPM Interrupt Configuration Register (CICR) The CPM interrupt configuration register (CICR) defines CPM interrupt request levels, the priority between the USB and SCCs, and the highest priority interrupt. MPC885 PowerQUICC Family Reference Manual, Rev. 2 35-6 Freescale Semiconductor...
Page 951 Highest priority. Specifies the 5-bit interrupt number of the CPIC interrupt source that is advanced to the highest priority in the table. These bits can be modified dynamically. (Programming HP = 0b11111 keeps PC15 the highest priority source for external interrupts to the core.) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 35-7...
Page 952 Acknowledge interrupts from port C by clearing the CIPR bit directly (by writing ones). For all other interrupt sources, however, clear the unmasked event register bits instead, thus causing the CIPR bit to be cleared. MPC885 PowerQUICC Family Reference Manual, Rev. 2 35-8 Freescale Semiconductor...
Page 953 The CPM interrupt vector register (CIVR) is used to identify an interrupt source. The core uses the IACK bit to acknowledge an interrupt. CIVR can be read at any time. This register is affected by HRESET and SRESET. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 35-9...
Page 954 4. Decide which events in the SCCE2 must be handled and clear those bits as soon as possible. SCCE bits are cleared by writing ones. 5. Handle the events in the SCC2 Rx BD or Tx BD tables. 6. Clear CISR[SCC2]. MPC885 PowerQUICC Family Reference Manual, Rev. 2 35-10 Freescale Semiconductor...
Page 955 7. Execute the rfi instruction. If any unmasked SCCE bits remain (either not cleared by the software or set by the MPC885 during the execution of this handler), this interrupt source is pending again immediately after the rfi instruction. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 35-11...
Page 956 CPM Interrupt Controller MPC885 PowerQUICC Family Reference Manual, Rev. 2 35-12 Freescale Semiconductor...
Page 957 ATM operations through both the UTOPIA and serial interfaces. • Chapter 43, “UTOPIA Interface,” describes how the MPC885 supports classic SAR MPHY ATM operation, including the UTOPIA modes and the signals provided for UTOPIA support. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor VI-1...
Page 958 (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table VI-1. Acronyms and Abbreviated Terms Term Meaning ATM adaptation layer AAL5 CPCS–PDU Available bit rate Allowed cell rate Arithmetic logic unit MPC885 PowerQUICC Family Reference Manual, Rev. 2 VI-2 Freescale Semiconductor...
Page 959 Register used for determining the source of a DSI exception Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory ESAR Enhanced segmentation and reassembly Free buffer pool FIFO First-in-first-out (buffer) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor VI-3...
Page 960 Machine state register Not a number NCITS Number of cells in a time slot Network interface card Network interface unit NMSI Nonmultiplexed serial interface Non-real time Operation Administration & Maintenance MPC885 PowerQUICC Family Reference Manual, Rev. 2 VI-4 Freescale Semiconductor...
Page 961 Serial peripheral interface SRAM Static random access memory SRTS Synchronous residual time stamp Transmit connection table Time-division multiplexed Terminal endpoint of an ISDN connection Translation lookaside buffer Time-slot assigner Transmit MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor VI-5...
Page 962 Virtual circuit identifier Virtual path Virtual path connection Virtual path identifier UTOPIA Universal test and operations physical interface for ATM Variable bit rate Virtual channel or virtual circuit Wide area network MPC885 PowerQUICC Family Reference Manual, Rev. 2 VI-6 Freescale Semiconductor...
Page 963 As an ATM Controller, the MPC885 is functionally the same as the standard MPC860. However, when running an ATM application, the MPC885 does use different pin multiplexing or loses some functionality depending on the ATM mode chosen. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 36-1...
Page 964 A detailed explanation of the technical reasons for these restrictions is provided in Section 40.4, “Using the APC Without Using SCC4 or UTOPIA.” There are no restrictions on SCC1–3; they can run any available communications protocol, including serial ATM. MPC885 PowerQUICC Family Reference Manual, Rev. 2 36-2 Freescale Semiconductor...
Page 965 – Reassembles CPCS_PDU directly to host memory – CRC32 check – CPCS_PDU padding removal – CS_UU, CPI, and LENGTH reporting – CLP and congestion reporting – Interrupt per buffer or per frame MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 36-3...
Page 966 – Supports UTOPIA level 2 multi-PHY interface for up to 31 PHYs – Supports 8-bit UTOPIA data bus (using eight shared data signals in muxed mode or using two separate 8-bit receive and transmit buses in split mode) MPC885 PowerQUICC Family Reference Manual, Rev. 2 36-4 Freescale Semiconductor...
Page 967 — Flexible, user-defined address compression mechanism — Content-addressable memory (CAM) 36.4 MPC885 Application Example Figure 36-1 shows a possible MPC885 configuration supporting both serial and UTOPIA ATM transmissions, and Fast Ethernet. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 36-5...
Page 968 In UTOPIA mode, the ATM controller handles transfers on a cell-by-cell basis. The UTOPIA interface implements a cell-level handshake. The supported bit rate of the UTOPIA interface is higher than that of serial ATM which additionally implements the transmission convergence (TC) layer. MPC885 PowerQUICC Family Reference Manual, Rev. 2 36-6 Freescale Semiconductor...
Page 969 PHY has a complete cell in its receive FIFO buffer. The ATM controller first receives the cell header through the UTOPIA interface. The receiver translates the header address (GFC/VPI/VCI/PTI) to a channel number using either a look-up table in dual-port RAM, address MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 36-7...
Page 970 For receiving, the expanded header of the last cell of the current connection is copied to the expansion field in the connection’s RxBD. MPC885 PowerQUICC Family Reference Manual, Rev. 2 36-8 Freescale Semiconductor...
Page 971 SCC to the dual-port RAM (DPR). The receiver translates the header address (VCI/VPI/PTI) to a channel number through either a look-up table in dual-port RAM, address compression tables in external MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 36-9...
Page 972 The ATM pace controller determines the next channel (or n channels) to be transmitted and writes the channel number of these channels in the transmit queue every APC slot time. The transmitter sends one cell for each channel entry in the transmit queue. MPC885 PowerQUICC Family Reference Manual, Rev. 2 36-10 Freescale Semiconductor...
Page 973 The PTP mechanism allows the user to implement ATM to ATM cell switching from one ATM port to another ATM port (including specific PHYs on the UTOPIA multi-PHY bus). Figure 36-3 shows an MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 36-11...
Page 974 36.12 General ATM Initialization Requirement All ATM parameter RAM areas and data structures, such as the connection tables and APC priority levels, should be cleared before beginning the actual system initialization process. MPC885 PowerQUICC Family Reference Manual, Rev. 2 36-12 Freescale Semiconductor...
Page 975 TxBD tables and buffers and their associated pointers for two example transmit channels, channel 1 and channel 4. (The RxBD tables and buffers for receive channels have the same structure.) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-1...
Page 976 48 bytes (that is, the value of SMRBLR in the SCC parameter RAM should be a multiple of 48). The buffers are filled with multiples of 48 bytes, except for the last buffer in a frame from which the AAL5 pads are removed. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-2 Freescale Semiconductor...
Page 977 Figure 37-3. ATM RxBD For UTOPIA operation, a global option to support expanded cells is available. ATM RxBDs in expanded cell mode are 24 bytes, as shown in Figure 37-4. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-3...
Page 978 1 Interrupt occurs after this buffer has been closed by the ATM controller. This class of interrupt is indicated through the setting of the RXB bit in an entry in the interrupt queue. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-4 Freescale Semiconductor...
Page 979 BD of the frame by the CP for channels that implement AAL5. Note that the whole received PDU is written to the data buffer even if a receive length error is detected. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-5...
Page 980 ATM Transmit Buffer Descriptors (TxBDs) The format of the ATM transmit buffer descriptor (TxBD) applies to both UTOPIA and serial ATM modes. ATM TxBDs are 12 bytes, as shown in Figure 37-5. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-6 Freescale Semiconductor...
Page 981 OFFSET + C CELL HEADER EXPANSION 1 OFFSET + 10 CELL HEADER EXPANSION 2 OFFSET + 14 CELL HEADER EXPANSION 3 Figure 37-6. ATM TxBD in Expanded Cell Mode (UTOPIA Only) MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-7...
Page 982 1 The CP does not clear TxBD[R] after this BD is closed, allowing the buffer to be resent the next time the CP accesses this BD. 7–12 — Reserved, should be cleared during initialization. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-8 Freescale Semiconductor...
Page 983 Transmit data Contains the address of the associated data buffer. The buffer may reside in buffer pointer either internal or external memory. This value is not modified by the CP. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-9...
Page 984 The CTs for internal channels (channels 0–31) are in the dual-port RAM. In extended channel mode (UTOPIA only), the tables for external channels (numbered 32 and above) are kept in external memory. The structure of the CTs is shown in Figure 37-7. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-10 Freescale Semiconductor...
Page 985 Receive Connection Table (RCT) Each receive connection table (RCT) holds parameters (channel configuration, pointers, status flags, and temporary data) for a single ATM receive channel. Figure 37-8 shows the RCT structure. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-11...
Page 986 NOTE: Do not set PM for the raw cell queue (RCT0). NOTE: To enable performance monitoring in general, activate the MCF by setting SRSTATE[MCF]; see Section 39.2, “Management Cell Filter (MCF).” 2–7 — Reserved, should be cleared during initialization. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-12 Freescale Semiconductor...
Page 987 PTP (AAL0 only). Port-to-port cell switching. Setting this bit turns a regular RCT into a PTP RCT, so it should be cleared in this context. 0 Normal AAL0 mode. 1 Activate the port-to-port switching mechanism. See Section 37.2.1.1, “Port-to-Port Protocol-Specific RCT.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-13...
Page 988 RAM) to the TSTAMP field on the arrival of the frame’s first cell. TSTAMP can be used to check for a time-out condition. Note that the time stamp is not supported in port-to-port mode. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-14 Freescale Semiconductor...
Page 989 The specific RCT format for a receive channel used in port-to-port switching is shown in Figure 37-9. It shows the AAL0 parameters which are valid in PTP mode (RCT[PTP] is set). See also Section 39.4, “Port-to-Port (PTP) Switching.” MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-15...
Page 990 Port-to-port cell switching. Setting this bit turns a regular RCT into a PTP RCT, so it should be set in this context. 0 Normal AAL0 mode. 1 Activate the port-to-port switching mechanism. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-16 Freescale Semiconductor...
Page 991 11 = Address translation on VPI and GFC only. The address translation header’s VPI and GFC replaces the VPI and GFC in original cell header. The VCI, PTI and CLP are preserved (copied from the original). MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-17...
Page 992 1st priority: APC_LEVEL = PHY n _pointer 2nd priority: APC_LEVEL = PHY n _pointer + (1 x 32) 3rd priority: APC_LEVEL = PHY n _pointer + (2 x 32) … MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-18 Freescale Semiconductor...
Page 993 The bitmask for header translation is used if the BATR bit is set.It is in little endian format. if bitwise address translation is not used, this field should be cleared. 0x1C–0x1F — — Reserved, should be cleared during initialization. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-19...
Page 994 This bit is used internally. 0 Idle state. No buffer is open for this channel. 1 Sending. The transmitter is in the middle of a frame; a transmit buffer is open. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-20 Freescale Semiconductor...
Page 995 Chapter 38, “ATM Parameter RAM.” Note that TBASE is a word-aligned offset pointer from TBDBASE; that is, it provides bits [14–29] of the offset, and bits [30–31] are always 00. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-21...
Page 996 0x3A — APCPR APC pace remainder. Contains the remainder of the rate generated by the APC after adding the pace FRACTION to the cumulative APCPR. Should be cleared during initialization. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-22 Freescale Semiconductor...
Page 997 For example, a pace of 1.5 is obtained by programming APCP to 1 and APCPF to 0x8000. The pace thus becomes 1+32768/65536, or a value of 1.5. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-23...
Page 998 This bit is used internally. 0 Idle state. No buffer is open for this channel. 1 Sending. The transmitter is in the middle of a frame; a transmit buffer is open. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-24 Freescale Semiconductor...
Page 999 Chapter 38, “ATM Parameter RAM.” Note that PTP_BASE is a word-aligned offset pointer from TBDBASE; that is, it provides bits [14–29] of the offset, and bits [30–31] are always 00. MPC885 PowerQUICC Family Reference Manual, Rev. 2 Freescale Semiconductor 37-25...
Page 1000 0x3A — APCPR APC pace remainder. Contains the remainder of the rate generated by the APC after adding the pace FRACTION to the cumulative APCPR. Should be cleared during initialization. MPC885 PowerQUICC Family Reference Manual, Rev. 2 37-26 Freescale Semiconductor...

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