Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 460

Memory Controller
Configuration
OR x SCCR OR x
Access
[TRLX] [EBDF] [CSNT]
1 Read x
Write
00
01
1
SCY is the number of wait cycles from the option register.
15.5.1.1 Chip-Select Assertion Timing
The banks selected by the GPCM support an option to output CS at different timings with respect to the
external address bus. Depending on the value of the ACS field (plus an additional cycle if TRLX = 1), CS
can be output as follows
• Simultaneous with the external address
• One quarter of a clock cycle later
• One half of a clock cycle later
Figure 15-16 shows a basic connection between the MPC885 and an external peripheral device. Here, CS
(the strobe output for the memory access) is connected directly to CE of the memory device and R/W is
connected to the respective R/W in the peripheral device.
15-20
Table 15-11. GPCM Strobe Signal Behavior (continued)
Address Address
OR x
to CS to OE
[ACS]
Asserted Asserted
x 00 0 3/4*Clk
10 1+1/4*Clk 1+3/4*Clk
11 1+1/2*Clk
0 00 0
10 1+1/4*Clk
11 1+1/2*Clk
1 00 0
10 1+1/4*Clk
11 1+1/2*Clk
00 0
10 1+1/4*Clk
11 1+1/2*Clk
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Signal Behavior
Address Data to
to WE WE
Asserted Asserted
x x
x 3/4*Clk -1/4*Clk
1+3/4*Clk 3/4*Clk
3/4*Clk -1/4*Clk
1+3/4*Clk 3/4*Clk
3/4*Clk -1/4*Clk
1+3/4*Clk 3/4*Clk
CS WE
Negated to Negated to Total
Address/ Address/ Cycles
Data Invalid Data Invalid
1/4*Clk x 2+2*SCY
3+2*SCY
1/4*Clk 2+2*SCY
3+2*SCY
1+1/2*Clk
1+1/2*Clk 4+2*SCY
1/4*Clk 1+3/8*Clk 3+2*SCY
1+3/8*Clk 4+2*SCY
Freescale Semiconductor