Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 776

SCC Ethernet Mode
Table 27-9. SCC Ethernet TxBD Status and Control Field Descriptions (continued)
Bits Name
8 LC Late collision. Set when a collision occurred after the number of bytes defined for PSMR[LCW] are
sent. The ethernet controller stops sending and writes this bit after it finishes sending the buffer.
9 RL Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully
transmit a message because of repeated collisions on the medium. The ethernet controller writes
this bit after it finishes attempting to send the buffer.
10–13 RC Retry count. Indicates the number of retries required before the frame was sent successfully. If RC
= 0, the frame was sent correctly the first time. If RC = 15 and RET_LIM = 15 in the parameter RAM,
15 retries were required. Because the counter saturates at 15, if RC = 15 and RET_LIM > 15, then
15 or more retries were required. The controller writes this field after it successfully sends the buffer.
14 UN Underrun. Set when the ethernet controller encounters a transmitter underrun while sending the
buffer. The ethernet controller writes UN after it finishes sending the buffer.
15 CSL Carrier sense lost. Set when carrier sense is lost during frame transmission. The ethernet controller
writes CSL after it finishes sending the buffer.
Data length and buffer pointer fields are described in
27.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
The SCC event register (SCCE) is used as the ethernet event register to generate interrupts and report
events recognized by the ethernet channel. When an event is recognized, the ethernet controller sets the
corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in
the ethernet mask register (SCCM). SCCE bits are cleared by writing ones; writing zeros has no effect. All
unmasked bits must be cleared before the CPM clears the internal interrupt request.
0
Field
Reset
R/W
Addr 0xA30 (SCCE2)/0xA34 (SCCM2); 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4)
Figure 27-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)
Figure 27-10 describes SCCE and SCCM fields.
Bits Name
0–7 — Reserved, should be cleared.
8 GRA Graceful stop complete. Set as soon the transmitter finishes any frame that was in progress when
a
GRACEFUL STOP TRANSMIT
9–10 — Reserved, should be cleared.
11 TXE Set when an error occurs on the transmitter channel.
12 RXF Rx frame. Set when a complete frame has been received on the ethernet channel.
27-20
—
0000_0000_0000_0000
Table 27-10. SCCE/SCCM Field Descriptions
command was issued. It is set immediately if no frame was in progress.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 21.3, "SCC Buffer Descriptors (BDs)."
7 8 9 10 11
GRA — TXE
R/W
Description
12 13 14 15
RXF BSY TXB RXB
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