Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 795

Chapter 29
Serial Management Controllers (SMCs)
The two serial management controllers (SMCs) are full-duplex ports that can be configured independently
to support one of three protocols—UART, transparent, or general-circuit interface (GCI). Simple UART
operation is used to provide a debug/monitor port in an application, which allows the SCCs to be free for
other purposes. The SMC in UART mode is not as complex as the SCC in UART mode. The SMC clock
can be derived from one of the four internal baud rate generators (BRGs) or from an external clock pin.
However, the clock should be a 16× clock.
In totally transparent mode, the SMC can be connected to TDM channel (such as a T1 line) or directly to
its own set of pins. The receive and transmit clocks are derived from the TDM channel, the internal BRGs,
or from an external 1× clock. The transparent protocol allows the transmitter and receiver to use the
external synchronization pin. The SMC in transparent mode is not as complex as the SCC in transparent
mode.
Each SMC supports the C/I and monitor channels of the GCI bus, for which the SMC connects to a
time-division multiplex (TDM) channel in the serial interface (SI).
describes GCI interface configuration.
The SMCs support loop-back and echo modes for testing. The SMC receiver and transmitter are
double-buffered, corresponding to an effective FIFO size (latency) of two characters.
the SMC block diagram.
Freescale Semiconductor
Control
Registers
Peripheral Bus
Rx
Data
Register
RXD
Shifter
Figure 29-1. SMC Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Chapter 20, "Serial Interface,"
SYNC
Control
Logic
CLK
Tx
Data
Register
TXD
Shifter
Figure 29-1 shows
29-1