Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 910

Parallel Interface Port (PIP)
Table 33-10. PIP RxBD Status and Control Field Descriptions
Bits Name
0 E Empty
0 The buffer associated with this descriptor is full or stopped receiving data because an error occurred. The
core can read or write any fields of this RxBD. The CP cannot use this BD while E is 0.
1 The buffer associated with this BD is empty or is receiving data. Once E is set, the core should not write
any fields of this RxBD.
1 — Reserved, should be cleared.
2 W Wrap (last buffer descriptor in RxBD table). The number of RxBDs in the table is determined only by the W
bit and space constraints of the dual-port RAM.
0 Not the last BD in the RxBD table.
1 The last BD in the RxBD table. After this BD is processed, the current RxBD pointer wraps to the top of
the RxBD table (RBASE).
3 I Interrupt
0 No interrupt is generated after this buffer is filled.
1 PIPE[RXB] is set when the CP fills this buffer, signaling the core to process the buffer. The RXB bit causes
an interrupt if not masked.
4 C Control character
0 This buffer does not contain a control character.
1 This buffer has a user-defined control character as its last byte.
5 — Reserved and should be cleared.
6 CM Continuous mode
0 Normal operation.
1 The E bit is not cleared by the CP after this buffer is closed, thus allowing the associated buffer to be
automatically overwritten the next time the CP processes this BD.
7 SL Silence. Indicates that the buffer has closed because the programmable silence period has timed-out.
8–15 — Reserved, should be cleared.
33.6 PIP CP Commands
The PIP transmit and receive CP commands are the same as the corresponding SMC2 commands (same
op-codes and channel number); see
transmit commands are described in
Command
Disables transmission of frames on the transmit channel. If the PIP controller receives this command during
STOP TRANSMIT
frame transmission, transmission stops and the TBPTR is not advanced to the next BD. No new BD is
accessed and no new buffers are sent for this channel. The transmitter idles until
Used to begin or resume sending using the current BD pointed to by TBPTR. When the channel receives this
RESTART
command after PIPC[STR] is set, it starts processing the current BD. The PIP controller expects
TRANSMIT
after
TRANSMIT
Initializes all transmit parameters in the PIP parameter RAM to their reset state and should be issued only
INIT TX
when the transmitter is disabled.
PARAMETERS
The PIP receive commands are described in
33-14
Section 18.5, "CPM Configuration Register (CPMCFG)."
Table 33-11.
Table 33-11. PIP Transmit CP Commands
is issued, or after a transmitter error occurs.
STOP TRANSMIT
Table 33-12.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Description
The PIP
is issued.
RESTART TRANSMIT
RESTART
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