Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 222

Instruction and Data Caches
3. Write the load-and-lock cache block command (IC_CST[CMD] = 0b011) to the IC_CST register.
4. Execute an isync instruction.
5. Repeat steps 2 through 4 to load and lock another cache block.
6. Read the IC_CST error type bits to determine if the sequence completed without errors.
After the load-and-lock cache block command is written to the IC_CST register, the cache checks if the
block containing the byte addressed by IC_ADR[ADR] is in the cache (hit). If it is in the cache, the block
is locked. If the block is not in the cache, a normal miss sequence is initiated (see
"Instruction Cache Miss,"
block is locked.
The user must check the IC_CST error type bits to determine if the load-and-lock cache block operation
completed without error. The load-and-lock cache block command generates two possible errors:
• Type 1—A bus error occurred in one of the fetch cycles
• Type 2—There is no available way to lock (It is the responsibility of the user to make sure that there
is at least one unlocked way in the appropriate set.)
The error type bits in the IC_CST register are sticky, thus allowing the user to perform a series of
load-and-lock cache block commands before checking the termination status. These bits are set by the
MPC885 and are cleared by software.
Note that the MPC885 considers all zero-wait-state devices on the internal bus as caching-inhibited. For
this reason, software should not perform load-and-lock cache block operations from these devices on the
internal bus.
7.3.1.2.3 Instruction Cache Unlock Cache Block Command
The unlock cache block command (IC_CST[CMD] = 0b100) is used to unlock previously locked cache
blocks. To unlock a cache block:
1. Write the address of the cache block to be unlocked to the IC_ADR register.
2. Write the unlock cache block command (IC_CST[CMD] = 0b100) to the IC_CST register.
If the block is found in the cache (hit), it is unlocked and thereafter operates as a regular valid cache block.
If the block is not found in the cache (miss), no operation is performed. There are no error cases for the
unlock block command.
The instruction cache performs the unlock cache block command in one clock cycle.
7.3.1.2.4 Instruction Cache Unlock All Command
The unlock all command (IC_CST[CMD] = 0b101) is used to unlock the entire instruction cache with a
single command.
When the unlock all command is performed, if a cache block is locked, it is unlocked and thereafter
operates as a regular valid cache block. If a block is not locked or if it is marked invalid, no operation is
performed. There are no error cases for the unlock all command
The instruction cache performs the unlock all command in one clock cycle.
7-10
for more information). After the addressed block is placed into the cache, the
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 7.5.2,
Freescale Semiconductor