Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 157

Table 3-5 summarizes MPC885 features with respect to the OEA definition.
Functionality
Machine state The floating-point exception mode (bits FE0 and FE1) is ignored by the MPC885. The IP bit initial
register state after reset is set as programmed by the reset configuration specified in
"System Reset Interrupt (0x00100)."
Processor The value of the PVR register's version field is 0x0050. The value of the revision field is 0x0000, and
version register it is incremented each time the device is revised, to allow software to distinguish between revisions.
Other OEA The following registers are not implemented: SDR1, BAT registers, segment registers, and EAR
registers
Page size The MPC885 differs from the OEA-defined memory management mode with respect to page sizes.
Page sizes are 4, 16, and 512 Kbytes, and 8 Mbytes with an optional subpage granularity of 1 Kbyte
for 4-Kbyte pages in a maximum physical memory size of 4 Gbytes. Neither ordinary nor direct-store
segments are supported.
Address space The MPC885 differs from the OEA-defined memory management model. Specifically, it does not
support the same address translation mechanism that requires an intermediate 52-bit virtual
address. It also does not support block address translation or the associated block address
translation SPRs. In its place, the MPC885's internal memory space includes memory-mapped
control registers and memory used by various modules on the chip. This memory is part of the main
memory as seen by the core but cannot be accessed by any external system device.
Address If address translation is disabled (MSR[IR] = 0 for instruction accesses or MSR[DR] = 0 for data
translation accesses), the EA is treated as the physical address and is passed directly to the memory
subsystem. Otherwise, the EA is translated by using the MMU's TLB mechanism. Instructions are
not fetched from no-execute or guarded memory and data accesses are not executed speculatively
to or from the guarded memory. The features of the MMU hardware are as follows:
• 32-entry fully-associative ITLB
• 32-entry fully-associative DTLB
• Supports up to 16 virtual address spaces
• Supports 16 access protection groups
• Supports fast software table search mechanism
The MPC885 MMU is described in detail in
Reference and No reference bit is supported by the MPC885. However, the change bit is supported by using the
change bits data TLB error exception mechanism when writing to an unmodified page.
Memory Two protection modes are supported by the MPC885:
protection • Domain manager mode
• PowerPC mode
See Chapter 8, "Memory Management Unit."
Freescale Semiconductor
Table 3-5. OEA-Level Features
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Chapter 8, "Memory Management Unit."
The MPC8xx Core
Section 6.1.2.1,
3-17