Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 262

Memory Management Unit
Table 8-12 describes MI_RPN fields.
protection modes.)
Bits Name
0–19 RPN Real (physical) page number
20–21 PP Protection attributes for
subpages 1–4.
Supervisor
00 No access
01 Executable
1x Executable
1
22 PP
23
24–25
26–27
28 SPS Small page size. Used with the level-one (L1) descriptor's page-size (PS) field; see
"Page Size."
0 4 Kbyte
1 16 Kbyte or larger (512 Kbyte or 8 Mbyte)
29 SH Shared page:
0 This entry matches only if ASID field in the TLB entry matches the value M_CASID.
1 ASID comparison is disabled for the entry.
30 CI Cache-inhibit attribute for the entry.
0 Caching is allowed.
1 Caching is inhibited.
31 V Entry valid indication.
1
For pages larger than 4 Kbytes in mode 2, PP in bits [22–23,24–25,26–27] must equal the PP in bits [20–21].
8.8.7 DMMU Real Page Number Register (MD_RPN)
The DMMU real page number register (MD_RPN), shown in
and the memory attributes of an entry to be loaded into a TLB. This register should be written after the
MD_EPN and MD_TWC registers.
8-20
(Section 8.5, "Protection Resolution Modes,"
Table 8-12. MI_RPN Field Descriptions
Mode 2
Extended Encoding:
Supervisor
User 00 No access
No access 01 Executable
No access 1x Reserved
Executable
0 Bits 20–21 contain basic encoding
1 Bits 20–21 contain extended encoding
Reserved
MD_CTR[PPCS] = 0
For 1-Kbyte pages in mode 3, set
to the appropriate subpage
validity. Otherwise, set to
0b1111.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
describes the
Mode 1 or Mode 3
Basic Encoding:
User Supervisor
No access 00 Executable
No access 01 Executable
Reserved 1x Executable
MD_CTR[PPCS] = 1
1000 Hit only for supervisor
accesses
0100 Hit only for user accesses
1100 Hit for both
Figure 8-12, contains the physical address
Freescale Semiconductor
User
No access
Executable
Executable
Section 8.7.3,