Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 436

Clocks and Power Control
Bits Name
17–18 DFSYNC Division factor for the SYNCCLK. This field sets the divout1, where divout1 is equivalent to JDBCK
divide by 2, frequency division factor for the SYNCCLK signal. Changing the value of this field
does not result in a loss-of-lock condition. This field is cleared by a power-on or hard reset.
00 Divide by 1 (normal operation).
01 Divide by 4.
10 Divide by 16.
11 Divide by 64.
19–20 DFBRG Division factor of the BRGCLK. This field sets the divout1, where divout1 is equivalent to JDBCK
divide by 2, frequency division factor for the BRGCLK signal. Changing the value of this field does
not result in a loss-of-lock condition. This field is cleared by a power-on or hard reset.
00 Divide by 1 (normal operation).
01 Divide by 4.
10 Divide by 16.
11 Divide by 64.
21–23 DFNL Division factor low frequency. Sets the divout1, where divout1 is equivalent to JDBCK divide by 2,
frequency division factor for general system clocks to be used in low-power mode. In low-power
mode, the MPC885 automatically switches to the DFNL frequency. To select the DFNL frequency,
load this field with the divide value and set the CSRC bit. A loss-of-lock condition will not occur
when changing the value of this field. This field is cleared by a power-on or hard reset.
000 Divide by 2.
001 Divide by 4.
010 Divide by 8.
011 Divide by 16.
100 Divide by 32.
101 Divide by 64.
110 Reserved.
111 Divide by 256.
24–26 DFNH Division factor high frequency. Sets the divout1, where divout1 is equivalent to JDBCK divide by
2, frequency division factor for general system clocks to be used in normal mode. In normal mode,
the MPC885 automatically switches to the DFNH frequency. To select the DFNH frequency, load
this field with the divide value and clear CSRC. A loss-of-lock condition does not occur when this
field is changed. This field is cleared by a power-on or hard reset.
000 Divide by 1.
001 Divide by 2.
010 Divide by 4.
011 Divide by 8.
100 Divide by 16.
101 Divide by 32.
110 Divide by 64.
111 Reserved.
27–29 DFUTP
UTOPIA clock dividers; see
30–31 DFAUTP
14-20
Table 14-8. SCCR Field Descriptions (continued)
Section 42.2, "UTOPIA Mode
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Registers."
Freescale Semiconductor