Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 561

• Bus monitoring—The restart gate mode can detect a signal that is abnormally stuck low. The bus
signal should be connected to TGATEx. The timer count is reset on the falling edge of the bus
signal and if the bus signal does not go high again within the number of user-defined clocks, an
interrupt can be generated.
The gate function is enabled in the TMR; the gate operating mode is selected in the TGCR.
Note that TGATEx is internally synchronized to the system clock. However, if TGATEx meets the
asynchronous input setup time, the counter begins counting after one system clock when the input clock
source (TMRx[ICLK]) is internal.
17.2.2.5 Cascaded Mode
Timer 1 can be internally cascaded to timer 2 and timer 3 can be internally cascaded to timer 4 to form
32-bit timers. The TGCR is used to put the timers into cascaded mode, as shown in
TRR, TCR, TCN connected to D[0–15]
TRR, TCR, TCN connected to D[0–15]
If TGCR[CASx] is set, the two corresponding timers function as a 32-bit timer with a 32-bit TRR, TCR,
and TCN. In this case, the mode registers TMR1 and TMR3 are ignored and TMR2 and TMR4 define the
mode. Similarly, the capture is controlled by TIN2 or TIN4, and interrupts are generated by TER2 or
TER4. In cascaded mode, the cascaded TRR, TCR, and TCN should always be accessed with 32-bit bus
cycles.
17.2.2.6 Timer 1 and SPKROUT
Timer 1 can be used to drive audio alerts through the PCMCIA SPKROUT signal. Enabling timer 1 results
in SPKROUT being driven with timer 1's frequency. Timer 1 is XORed with the 4 SPKR_B input signals
to generate SPKROUT.
To prevent timer 1 from affecting SPKROUT, either use the timer in a pulse mode or do not enable it.
17.2.3 CPM Timer Register Set
The following subsections discuss the CPM timer register set.
Freescale Semiconductor
Timer 1
Capture
Timer 3
Capture
Figure 17-4. Timer Cascaded Mode Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Communications Processor Module and CPM Timers
Timer 2
TRR, TCR, TCN connected to D[16–31]
Timer 4
TRR, TCR, TCN connected to D[16–31]
Figure 17-4.
Clock
Clock
17-7