Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 49

Figure
Number
1-1 MPC866P Block Diagram ...................................................................................................... 1-7
1-2 MPC885 Block Diagram......................................................................................................... 1-8
1-3 MPC866P Block Diagram ...................................................................................................... 1-9
1-4 MPC880 Block Diagram....................................................................................................... 1-10
1-5 MPC866P Block Diagram .................................................................................................... 1-12
1-6 MPC866P Block Diagram .................................................................................................... 1-13
1-7 MPC875 Block Diagram....................................................................................................... 1-13
1-8 MPC866P Block Diagram .................................................................................................... 1-14
1-9 MPC870 Block Diagram....................................................................................................... 1-15
1-10 Security Engine Functional Blocks....................................................................................... 1-17
3-1 Block Diagram of the Core ..................................................................................................... 3-4
3-2 Instruction Flow Conceptual Diagram .................................................................................... 3-6
3-3 Basic Instruction Pipeline Timing........................................................................................... 3-7
3-4 Sequencer Data Path ............................................................................................................... 3-8
3-5 LSU Functional Block Diagram ........................................................................................... 3-11
4-1 Condition Register (CR) ......................................................................................................... 4-2
4-2 XER Register .......................................................................................................................... 4-3
4-3 Machine State Register (MSR) ............................................................................................... 4-7
6-1 Exception Latency................................................................................................................. 6-18
7-1 MPC885 Instruction Cache Organization ............................................................................... 7-3
7-2 MPC885 Data Cache Organization......................................................................................... 7-5
7-3 Instruction Cache Control and Status Register (IC_CST) ...................................................... 7-6
7-4 Instruction Cache Address Register (IC_ADR)...................................................................... 7-7
7-5 Instruction Cache Data Port Register (IC_DAT) .................................................................... 7-8
7-6 Data Cache Control and Status Register (DC_CST)............................................................. 7-11
7-7 Data Cache Address Register (DC_ADR) ............................................................................ 7-13
7-8 Data Cache Data Port Register (DC_DAT)........................................................................... 7-13
7-9 Instruction Cache Data Path.................................................................................................. 7-20
8-1 Read/Instruction Fetch Flow Diagram .................................................................................... 8-4
8-2 Flow of Load/Store Access ..................................................................................................... 8-5
8-3 Effective-to-Physical Address Translation for 4-Kbyte Pages Block Diagram ...................... 8-6
8-4 Two-Level Translation Table (MD_CTR[TWAM] = 1) ......................................................... 8-9
8-5 Two-Level Translation Table (MD_CTR[TWAM] = 0) ....................................................... 8-10
8-6 IMMU Control Register (MI_CTR) ..................................................................................... 8-14
8-7 DMMU Control Register (MD_CTR) .................................................................................. 8-15
8-8 IMMU/DMMU Effective Page Number Register (Mx_EPN).............................................. 8-16
8-9 IMMU Tablewalk Control Register (MI_TWC)................................................................... 8-17
8-10 DMMU Tablewalk Control Register (MD_TWC)................................................................ 8-18
Freescale Semiconductor
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Title
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
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