Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 205

Table 6-13. Register Settings After an Instruction TLB Miss Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 0–3 0
4 1
10 1
11–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Other 0
Some instruction TLB registers are set to the values described in
Execution resumes at offset 0x01100 from the base address indicated by MSR[IP].
6.1.3.3 Data TLB Miss Exception (0x01200)
This type of exception occurs when MSR[DR] = 1 and an attempt is made to access a page whose effective
page number cannot be translated by TLB.
Table 6-14. Register Settings After a Data TLB Miss Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 1–4 0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Other 0
Some instruction TLB registers are set to the values described in
Execution resumes at offset 0x01200 from the base address indicated by MSR[IP].
6.1.3.4 Instruction TLB Error Exception (0x01300)
This type of exception occurs as a result of one of the following conditions if MSR[IR] = 1:
• The EA cannot be translated. Either the segment or page valid bit of this page is cleared in the
translation table. Note that although the MPC885 does not implement segment registers as they are
defined by the OEA, the concept of segment is retained as the memory space accessible to the
level-one table descriptors.
• The fetch access violates memory protection.
• The fetch access is to guarded memory.
Freescale Semiconductor
Table 6-14
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Setting
Chapter 8, "Memory Management Unit."
shows the following set registers:
Setting
Chapter 8, "Memory Management Unit."
Exceptions
6-13