Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 244

Memory Management Unit
— Software tablewalk updates supported by DTLB and ITLB miss exceptions and SPRs
— Each entry can be programmed to match user or supervisor accesses or both.
— Entries in each TLB can optionally be locked to ensure fast translation for selected regions.
• High performance
— 1 clock (zero wait state) access for a data cache hit and for an instruction cache hit when the
access is from the same page as the previous access
— 1 clock penalty for other TLB hit instruction accesses
• Low power consumption
8.2 PowerPC Architecture Compliance
The MPC885 core complies largely with the MMU as it is defined by the OEA, with the following
differences:
• The MPC885 does not implement the following PowerPC features:
— Block-address translation
— The optional direct-store functionality
— The memory coherency attribute
• The MPC885 supports the following additional features not defined by the PowerPC architecture:
— Variable page sizes. The OEA defines 4-Kbyte pages only
— Programmable defaults for write-through and cache-inhibited memory attributes when
translation is disabled.
— Additional registers and exceptions for handling table walks in software.
Note that although the MPC885 does not define segment registers as they are defined by the OEA, the
concept of segment is retained as the memory space accessible to the level-one table descriptors.
8.3 Address Translation
The core generates 32-bit effective addresses (EA) for memory accesses. Setting MSR[IR] and MSR[DR]
enables the effective-to-real translation for instruction fetching and data accesses, respectively.
Section 8.3.1, "Translation Disabled,"
"Translation Enabled," describes behavior when translation is enabled.
8.3.1 Translation Disabled
Because the IMMU and DMMU are separate, translation can be disabled or enabled independently for data
and instruction accesses by clearing MSR[DR] and MSR[IR], respectively. When translation is disabled,
the effective address is also the physical address.
Because the page translation mechanism is not used, the protection attributes that are part of the page table
structure cannot be used, so defaults are used. The default for whether accesses are cache-inhibited are
programmed through Mx_CTR[CIDEF]. Data accesses can be either write-through (memory writes go
both to the cache and to external memory) or write-back (memory writes directly affect the cache only and
8-2
describes behavior when translation is disabled.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 8.3.2,
Freescale Semiconductor