Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 438

Clocks and Power Control
Bits Name
12–15 MFI Integer part of the multiplication factor in the formula for the output frequency of the DPLL and
Interface. The range of values for the MFI is 5 to 15.
Refer to
16 — Reserved
17 TEXPS Timer expired status. Internal status bit set when the periodic timer expires, the timebase clock
alarm sets, the decrementer interrupt occurs, or the system resets.
This bit is cleared by writing a 1; writing a zero has no effect.
0 TEXP is negated.
1 TEXP is asserted.
18 — Reserved, should be cleared.
19 – Reserved, should be cleared.
20 — Reserved, should be cleared.
21 CSRC Clock source. Specifies whether DFNH or DFNL generates the general system clock. Cleared by
hard reset.
0 The general system clock is generated by the DFNH field.
1 The general system clock is generated by the DFNL field.
22–23 – Reserved, should be cleared.
24 CSR Checkstop reset enable. Enables an automatic reset when the processor enters checkstop mode. If
the processor enters debug mode at reset, reset is not generated automatically; refer to
See Section 53.5.2.2, "Debug Enable Register (DER)."
25 — Reserved, should be cleared.
26 FIOPD Force I/O pull down. Indicates when the address and data external pins are driven by an internal
pull-down device in sleep and deep-sleep mode.
0 No pull-down on the address and data bus.
1 Address and data bus is driven low in sleep and deep-sleep mode.
27-30 PDF Predivision factor minus 1 in the formula for the output frequency of the DPLL and Interface. The
range of values for the PDF is 0 to 15.
Refer to
31 DBRM DPLL BRM Order bit
O 0 First Order (should be used when fractional part, MFN/MFD, in undivisible form is greater than
1/10)
1 Second Order (should be used when fractional part, MFN/MFD, in undivisible form is less than
1/10)
This bit is ignored if the MFN is zero.
1
The total multiplication factor, including both the integer and fractional parts, must be between 5 to 15.
14-22
Table 14-9. PLPRCR Field Descriptions (continued)
Section 14.2.2, "Digital Phase Lock Loop and Interface."
Section 14.2.2, "Digital Phase Lock Loop and Interface."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
1
If the MFI is less than 5, the DPLL uses 5.
Table 14-10.
Freescale Semiconductor