Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 430

Powerquicc family

Table of Contents

Clocks and Power Control

management controllers to continue operating at a fixed frequency, even when the rest of the MPC885 is

operating at a reduced frequency.

SYNCCLK defaults to divout1, where divout1 is equivalent to JDBCK divide by 2, but can be reduced in

frequency by a frequency divider. This frequency divider is controlled by SCCR[DFSYNC].

The synchronization clock frequency is:

Limitations on SYNCCLK include:

SYNCCLK must always have a frequency at least as high as GCLKx.

SYNCCLK must and be at least two times the maximum serial clock rate used by the serial ports

in the system.

If the time-slot assigner (TSA) is used, SYNCCLK must be at least 2.5 times the maximum serial

clock rate of the TSA.

PIT Clock (PITCLK)

The PIT clock is generated either from EXTCLK or the crystal oscillator circuit (OSCM). This input

source can be divided by either 4 or 512. The PITCLK source and divide factor are selected by

SCCR[PTSEL] and SCCR[PTDIV].

The MODCK[1:2] state at PORESET negation determines the input clock source and prescalar value for

PITCLK. These values can be changed after reset by manipulating the associated bits in the SCCR.

Note: Since OSCM just uses one frequency input of 10 MHz, it is not possible to get a PITCLK period of 1 second.

This could however be achieved by giving an appropriate input to the EXTCLK.

Figure 14-10. SYNCCLK Divider

Table 14-5. PITCLK Configuration at PORESET

PITCLK Prescaler

MPC885 PowerQUICC Family Reference Manual, Rev. 2

divout1 freq

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PITCLK Input Source

OSCM (crystal oscillator)

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